From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2BAAD20347160 for ; Thu, 26 Oct 2017 08:06:44 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id 196so19701873wma.1 for ; Thu, 26 Oct 2017 08:10:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=NDp0L1YtKlpRoZWTDOBGXmho1NRTRxGR2tFtPHEeojs=; b=X37kHB3huLDf9RIbWkLWqg6r21oZe0Z7Ff4F13Wtj4rfIKxxPga3QRm+jgH8kiZkoR fPJmhnD2U3b9l4ht0J07aZWSjTf9nmveLedYvKWSeChU15Lh37KoDqvodgjtn4rlcqIw jAzS3ukjLRt8uYJVCOEHxtKNpNIOVps4cWnk4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=NDp0L1YtKlpRoZWTDOBGXmho1NRTRxGR2tFtPHEeojs=; b=rqvTjkco5sMPlWemmstRvkt/Nbj06ims5aJhjD6Adkml/CKIMKJHrSHGDxK8g9G9o7 DyHdQyIldIcn4UwufUy3s8mQL4cAmLezTm6cS2IBJviUmlBGjFlx6jUAMvVCSrMsrFQn ys0HkbQ8PAfOnpbo2o/lt6mOiQ4PULV2WV6IC0Wpsh2CWI2/DcdNizGdl0lZ7NZIllaC 0wwoHskRlukoX+ZnO/40TxCT1SPFGnJO4SAaNzPEeZ9u/zrrlrgucBTgWLCMYvLuRoUT KNVGgBcny7r9TPYJKvovCDN9gszJCNsgkS24l5faaN/cZT0rCF3psUybBtORVVngwTmw YuZQ== X-Gm-Message-State: AMCzsaV53QL0uQ2V1TWdEmXswgDXoC1ByB7e5y91QmYKjTPV+Ryf6+0d uFaOq/J6qvSx7UfH8rpsy3nOYg== X-Google-Smtp-Source: ABhQp+TQ+nSflcRho55rjDOA+VCTJAI2iys/rgHKRPR5McvwzUQYeBqsoOFNGmhFunoWuvJTUVFWnA== X-Received: by 10.28.184.143 with SMTP id i137mr1953308wmf.143.1509030629794; Thu, 26 Oct 2017 08:10:29 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id g16sm6077386wrd.72.2017.10.26.08.10.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 08:10:28 -0700 (PDT) Date: Thu, 26 Oct 2017 16:10:27 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171026151027.p6er7jcvjcsrmthq@bivouac.eciton.net> References: <20171025175947.22798-1-ard.biesheuvel@linaro.org> <20171025175947.22798-7-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171025175947.22798-7-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 06/23] Silicon/SynQuacer: implement PciHostBridgeLib support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 15:06:45 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote: > Implement the glue library that exposes the PCIe root complexes to > the generic PCI host bridge driver. Since that driver is the first > one to access the PCI config space, put the low level init code for > the RCs into this library's constructor. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 220 +++++++++++ > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 50 +++ > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 388 ++++++++++++++++++++ > 3 files changed, 658 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c > new file mode 100644 > index 000000000000..3937e98c0213 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c > @@ -0,0 +1,220 @@ > +/** @file > + PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC > + > + Copyright (c) 2017, Linaro Ltd. All rights reserved.
> + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + 0 > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + 1 > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + } > +}; > + > +GLOBAL_REMOVE_IF_UNREFERENCED > +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > + L"Mem", L"I/O", L"Bus" > +}; > + > +STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { > + { > + 0, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes > + { SYNQUACER_PCI_SEG0_BUSNUM_MIN, > + SYNQUACER_PCI_SEG0_BUSNUM_MAX }, // Bus > + { SYNQUACER_PCI_SEG0_PORTIO_MIN, > + SYNQUACER_PCI_SEG0_PORTIO_MAX }, // Io > + { SYNQUACER_PCI_SEG0_MMIO32_MIN, > + SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem > + { SYNQUACER_PCI_SEG0_MMIO64_MIN, > + SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > + }, { > + 1, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes > + { SYNQUACER_PCI_SEG1_BUSNUM_MIN, > + SYNQUACER_PCI_SEG1_BUSNUM_MAX }, // Bus > + { SYNQUACER_PCI_SEG1_PORTIO_MIN, > + SYNQUACER_PCI_SEG1_PORTIO_MAX }, // Io > + { SYNQUACER_PCI_SEG1_MMIO32_MIN, > + SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem > + { SYNQUACER_PCI_SEG1_MMIO64_MIN, > + SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + } > +}; > + > +/** > + Return all the root bridge instances in an array. > + > + @param Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + The array should be passed into PciHostBridgeFreeRootBridges() > + when it's not used. > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + OUT UINTN *Count > + ) > +{ > + *Count = ARRAY_SIZE (mPciRootBridges); > + > + return mPciRootBridges; > +} > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > + ) > +{ > +} > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param HostBridgeHandle Handle of the Host Bridge. > + @param Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + .SubmitResources(). > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); > + > + RootBridgeIndex = 0; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); > + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > + } > + } > + // > + // Skip the END descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > +} > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf > new file mode 100644 > index 000000000000..fca62b2577da > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf > @@ -0,0 +1,50 @@ > +## @file > +# PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC > +# > +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010019 > + BASE_NAME = SynQuacerPciHostBridgeLib > + FILE_GUID = fdc92446-65bc-4f86-b4a0-014a2119a732 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER > + CONSTRUCTOR = SynQuacerPciHostBridgeLibConstructor > + > +# > +# The following information is for reference only and not required by the build > +# tools. > +# > +# VALID_ARCHITECTURES = AARCH64 So, this is still marked as AARCH64-only, even though the platform is marked |ARM? / Leif