From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AA8E72035261E for ; Thu, 26 Oct 2017 14:31:48 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id 131so136591wms.0 for ; Thu, 26 Oct 2017 14:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=HnERz2CJiP9qflbfR5h83WZdpeSUtL1AI4PFHeset48=; b=ZGsDTc0uGa9g2W3CS5QmR8cDBkrLqAPHxEXrELUGofQAPg9bsvWNR9p4LCKsdGj3BV 8KrXpNonTJ3k/5pH4q2nBMSqzvz6f3IeRio+XA4AjYhK+vE2HWl4VCSONZORXqoJLlPK nx55P8kws5UblFDWo4+4XHZJCYCbtszYiGJ+0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HnERz2CJiP9qflbfR5h83WZdpeSUtL1AI4PFHeset48=; b=NvqyB9HIPdqjzs9VAxUPLr93D88rZjDxBuoJMPIVaUrjWH6bOMcFUglPKoPOr0U7FH zRl3oVaiWLUzmpy9IgPzUK/0NUY5VtmZwE92WOjmGB3TMfCqnjToVF/nXg//j6hkjDtr cJEKT3BNLph8P3ycCbaTbpp0ptazwhdQOXL1EAF1TOZV05FmwAWhcvZQN17bQeXYe1Es 0pPEV3g+IW5QW0ZI/EKkrBmnRGncLl0Ho0z/J0P3QGZhms8cq6dbXOv0tQCLn0SOniLZ NFrlGV0rEN1XMi6P1EBJJbDTS7i0vAmu5nuzPFWqWq4spGE/5lI3yv/BKt7mcUzTVF15 z9tg== X-Gm-Message-State: AMCzsaUIEIfkFkjq7MoP/uDrwkIXL+U+IWhuhO91840RVPGKT+29tX3V CqaxM9BeZNTjvOVdOo7R/BhGvQ== X-Google-Smtp-Source: ABhQp+QrKLcTIZef91GV/q9ccS5FKdHxpfq/riBsSgn3XbVWHbzGz7hiB8msADc8p8aEs2O57VIr6g== X-Received: by 10.28.161.1 with SMTP id k1mr185771wme.68.1509053733902; Thu, 26 Oct 2017 14:35:33 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id w206sm111004wmd.36.2017.10.26.14.35.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 14:35:32 -0700 (PDT) Date: Thu, 26 Oct 2017 22:35:31 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171026213531.blrrnc6zacptgbo3@bivouac.eciton.net> References: <20171025175947.22798-1-ard.biesheuvel@linaro.org> <20171025175947.22798-22-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171025175947.22798-22-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 21/23] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 21:31:49 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 25, 2017 at 06:59:45PM +0100, Ard Biesheuvel wrote: > Implement workaround suggested by Socionext to get legacy endpoints with > 32-bit BARs working. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel This was the modification that made the Developerbox onboard AHCI work? Worth mentioning explicitly if so. Regardless: Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 3c6eff602f74..dd6c9bf90223 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -31,10 +31,13 @@ > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 > #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 > +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 > > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 > #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF > +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF > > #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C > #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 > @@ -296,8 +299,9 @@ PciInitController ( > RootBridge->Mem.Base, > RootBridge->Mem.Base, > RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, > - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, > - 0); > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, > + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); > > // Region 1: Type 0 config space > ConfigureWindow (DbiBase, 1, > -- > 2.11.0 >