From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=chris.ruffin@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B3E522034A870 for ; Thu, 26 Oct 2017 18:00:45 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP; 26 Oct 2017 18:04:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,302,1505804400"; d="scan'208";a="167663417" Received: from cruffin-desk1.amr.corp.intel.com ([10.242.64.69]) by fmsmga005.fm.intel.com with ESMTP; 26 Oct 2017 18:04:31 -0700 From: Chris Ruffin To: edk2-devel@lists.01.org Date: Thu, 26 Oct 2017 21:04:29 -0400 Message-Id: <20171027010429.41540-1-chris.ruffin@intel.com> X-Mailer: git-send-email 2.13.3.windows.1 Subject: [PATCH] MdePkg/Include: fix incorrect structure definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 01:00:45 -0000 Fix incorrect structure definitions for PCI_REG_PCIE_SLOT_CONTROL in PciExpress21.h. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin --- MdePkg/Include/IndustryStandard/PciExpress21.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index ce9c06a7c6..d90b5975ba 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -182,18 +182,18 @@ typedef union { typedef union { struct { - UINT32 AttentionButtonPressed : 1; - UINT32 PowerFaultDetected : 1; - UINT32 MrlSensorChanged : 1; - UINT32 PresenceDetectChanged : 1; - UINT32 CommandCompletedInterrupt : 1; - UINT32 HotPlugInterrupt : 1; - UINT32 AttentionIndicator : 2; - UINT32 PowerIndicator : 2; - UINT32 PowerController : 1; - UINT32 ElectromechanicalInterlock : 1; - UINT32 DataLinkLayerStateChanged : 1; - UINT32 Reserved : 3; + UINT16 AttentionButtonPressed : 1; + UINT16 PowerFaultDetected : 1; + UINT16 MrlSensorChanged : 1; + UINT16 PresenceDetectChanged : 1; + UINT16 CommandCompletedInterrupt : 1; + UINT16 HotPlugInterrupt : 1; + UINT16 AttentionIndicator : 2; + UINT16 PowerIndicator : 2; + UINT16 PowerController : 1; + UINT16 ElectromechanicalInterlock : 1; + UINT16 DataLinkLayerStateChanged : 1; + UINT16 Reserved : 3; } Bits; UINT16 Uint16; } PCI_REG_PCIE_SLOT_CONTROL; -- 2.13.3.windows.1