From: Daniil Egranov <daniil.egranov@arm.com>
To: edk2-devel@lists.01.org
Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org,
Daniil Egranov <daniil.egranov@arm.com>
Subject: [PATCH 1/4] Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations
Date: Fri, 27 Oct 2017 00:33:23 -0500 [thread overview]
Message-ID: <20171027053326.48815-2-daniil.egranov@arm.com> (raw)
In-Reply-To: <20171027053326.48815-1-daniil.egranov@arm.com>
The ATA pass through read should use PCI IO bus master write operation
and ATA pass through write should use PCI IO bus master read operation
as the read and write operations executed from the bus master's point
of view.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
---
EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
index 2fb5fd68db..a938563ebd 100644
--- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
+++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
@@ -104,7 +104,7 @@ SiI3132AtaPassThruCommand (
}
Status = PciIo->Map (
- PciIo, EfiPciIoOperationBusMasterRead,
+ PciIo, EfiPciIoOperationBusMasterWrite,
Packet->InDataBuffer, &InDataBufferLength, &PhysInDataBuffer, &PciAllocMapping
);
if (EFI_ERROR (Status)) {
@@ -139,7 +139,7 @@ SiI3132AtaPassThruCommand (
OutDataBufferLength = Packet->OutTransferLength * SataDevice->BlockSize;
Status = PciIo->Map (
- PciIo, EfiPciIoOperationBusMasterWrite,
+ PciIo, EfiPciIoOperationBusMasterRead,
Packet->OutDataBuffer, &OutDataBufferLength, &PhysOutDataBuffer, &PciAllocMapping
);
if (EFI_ERROR (Status)) {
--
2.11.0
next prev parent reply other threads:[~2017-10-27 5:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-27 5:33 [PATCH 0/4] SataSiI3132Dxe fixes Daniil Egranov
2017-10-27 5:33 ` Daniil Egranov [this message]
2017-10-27 9:22 ` [PATCH 1/4] Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations Ard Biesheuvel
2017-10-27 5:33 ` [PATCH 2/4] Drivers/SataSiI3132Dxe: Allow 64-bit DMA transfer Daniil Egranov
2017-10-27 9:23 ` Ard Biesheuvel
2017-10-27 5:33 ` [PATCH 3/4] Drivers/SataSiI3132Dxe: Enable multi-controller support Daniil Egranov
2017-10-27 12:42 ` Ard Biesheuvel
2017-10-27 5:33 ` [PATCH 4/4] Drivers/SataSiI3132Dxe: Fixed startup and shutdown procedures Daniil Egranov
2017-10-27 12:47 ` Ard Biesheuvel
2017-10-27 12:48 ` [PATCH 0/4] SataSiI3132Dxe fixes Ard Biesheuvel
2017-10-27 16:57 ` Jeremy Linton
2017-10-27 17:00 ` Ard Biesheuvel
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