From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 26F3D2034A890 for ; Fri, 27 Oct 2017 07:33:37 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id n74so1863378wmi.1 for ; Fri, 27 Oct 2017 07:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=b+x9gLCmOnnvMNnrLGi0SQ6l2Ze8LUVTouBb90swlpg=; b=bGQS+KOuSEt6qGqlM31ml3TDcMXa6o4EhicTRPB8wUZKygLm1FkuRdPDVbZSYwBw0b jGYYjrTr0ujPREztjn0if0U9txs9tNGbydTDHiOjolRsv7gnrTPEZZRcB3oOtIrReJhV 8KeOVJUW4MK2im2n7EiPOID8xUmK7jsnc4oDw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=b+x9gLCmOnnvMNnrLGi0SQ6l2Ze8LUVTouBb90swlpg=; b=AAIPlVGOEag8AnhUeaObKPliGSYQph09RDWJGYoViBMkvKX9XMqrsUDNQ8GLM2Jrec Z77DfvgjHJhcboAWDWRhSwr4XieTkL+lartmbseisQcaKwbit7WiqTooWjvX+bQ9eAaJ uf3ec4VVxzU+c11FEhQre6pWA0t1XcCvLW2T+LSnF0NZBkCVi+hMpAHJKIvNvxOQkmJp RGZXmNr+5l73PNRLZ8m332z+cflr4WEokGCkm9DLiYB3ilfAOxfoiWqJQtDHURdVWlps EttVpYPJq9JddEt/XAeBDkOU4LPAXDz7mEHOyH05oVnf13vWGmOccg89283bki0969rQ vKKg== X-Gm-Message-State: AMCzsaXZd7sXX61zjROCVg0mOhdTtkVulIHCoJWnBAH4BddpEeK43D/E pMDl7AOq+lpTWbZN0BVCf860Pw== X-Google-Smtp-Source: ABhQp+SW7f+6eWhWeJgbNwqCDfYaS8eejBfj6NbF5pMjN8813aQ6ixu9ka09bRkxZiK0OpXi4LAs9w== X-Received: by 10.28.27.194 with SMTP id b185mr575405wmb.21.1509115043217; Fri, 27 Oct 2017 07:37:23 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l7sm6117752wrg.69.2017.10.27.07.37.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 07:37:22 -0700 (PDT) Date: Fri, 27 Oct 2017 15:37:20 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171027143720.txem665p5ax44urv@bivouac.eciton.net> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> <1509066832-5285-9-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1509066832-5285-9-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v2 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 14:33:37 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Oct 27, 2017 at 03:13:50AM +0200, Marcin Wojtas wrote: > This patch fixes incorrect settings for UHS mode in > SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which > the latter was missing. This field should be set to: > > 0x4 for DDR52 > 0x2 for SDR50 > 0x1 for SDR25 > 0x0 for others. > > This way EmmcSwitchToHighSpeed function is on par with Linux > set_uhs_signaling routine in the Xenon driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > index 3f73194..4d4833f 100755 > --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( > if (IsDdr) { > HostCtrl2 = BIT2; > } else if (ClockFreq == 52) { > + HostCtrl2 = BIT1; > + } else if (ClockFreq == 26) { > HostCtrl2 = BIT0; > } else { > HostCtrl2 = 0; > -- > 2.7.4 >