From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 05D7E2035D10D for ; Tue, 31 Oct 2017 03:49:37 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id z55so15530354wrz.1 for ; Tue, 31 Oct 2017 03:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=its2kpmC9jMrjP++ef6qSkrsn5mU0zjDLrsOXXhd76s=; b=IyY0/8acVfrqxVtCky5ejxVC72RN2mxkzg6RxYkk/GzPGd0MyIsrpfpuULcQZ0FGpE ioqbxApQgDEW3yIj1ogmHb2Gpn7Q1rA7/VQ1ASXOgA0mAed9s/V+YURktnB0L+CTMYqu UWbxoJ1EmCCzIWx6hAEpHZErTT0xPvfI0Rtqw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=its2kpmC9jMrjP++ef6qSkrsn5mU0zjDLrsOXXhd76s=; b=Z6btwKOCdH7VOMXm8YilY+GERNMJILbYQkAKT9wfNU5n40oJaZ6k6sI7v2yENOzs5D HW6DzYiUIALSVWr5azysSrDt8Kz6i0cMyS8uScEcYSwBqkK1gYI1hle8MstqLfn/Rniu 8AZBXEnVt+To4svxWH+JBsjFlqGdxPig6fC9pIYUdcYke1F4jmaWR/vE/Q3CwrZZSCOU ASQ7p0PhkWkzooAXmgxyj4erLvd3KTCuO/T6WrmWZnn1XJmG/kev44yYMRZTUos+F09M Gvz1bLb93erDtLtkktnCaxuayWTDJgn5kspGY5kgemmDsbXxjmA93Yhl4vrJ7DioqS1n Lc2Q== X-Gm-Message-State: AMCzsaX9cC/kyOzdjlAR5436Y6rN4bJTy8LXZCVO0qB3mBGeZ4xA1GDM SXXWztcxZpdlqgvK5K5TmfYpY0xtwVg= X-Google-Smtp-Source: ABhQp+T/TddCQfIYACFInTGl5sa1+93izerAI8L2WX2xq8MdhztvpzmYLBrTSTOozXYZQZyIWrqUpQ== X-Received: by 10.223.147.135 with SMTP id 7mr1469606wrp.237.1509447207154; Tue, 31 Oct 2017 03:53:27 -0700 (PDT) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id o14sm460985wra.54.2017.10.31.03.53.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:53:26 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: graeme.gregory@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com, Ard Biesheuvel Date: Tue, 31 Oct 2017 10:52:14 +0000 Message-Id: <20171031105218.30208-24-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171031105218.30208-1-ard.biesheuvel@linaro.org> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v3 23/27] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Oct 2017 10:49:37 -0000 Implement workaround suggested by Socionext to get legacy endpoints with 32-bit BARs working. This fixes the issue on Developer Box with the onboard ASM1061 SATA controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index b5bfea8e0e75..1bbef5b6cf98 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -32,10 +32,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 @@ -297,8 +300,9 @@ PciInitController ( RootBridge->Mem.Base, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); // Region 1: Type 0 config space ConfigureWindow (DbiBase, 1, -- 2.11.0