From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 31D6020352614 for ; Tue, 31 Oct 2017 20:50:29 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id r196so2518383wmf.2 for ; Tue, 31 Oct 2017 20:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=XToF8C2Pn5fLKRRfQGwAUwxXy75E+W5gJPVGP8oZZrY=; b=ZGTqfc3308DchMZpBmimG6UsiUxUC0EZlXk6Ttk9qUjm6yU13khTt46U1JJjDmag9l LD8o2uLkDmcem3kTBV20H5JeziS/klcClVi3ZxcbBLYEE3jxHw5z060aWYcOIzHjgZ/6 ZKkVCIJqMXHoyrMlNF7c4TPoxDj5E4BKrcy5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=XToF8C2Pn5fLKRRfQGwAUwxXy75E+W5gJPVGP8oZZrY=; b=pNVRRtPsgvCc0CMHR8oj7DILpCn9MYSb9qScwq+JTJMIShaE6XwAzMOzUvyw4rg7Tl 1Pc7i9k79k44JlJ7RNy/2D9ZHJGXxSIN43IoHWYsp9kMLtNCi+1XyZ4gYnqrmqR2aLDd Yl4/QBOHT8TIEZrRIzHtlC/lvPabQnIXbunkzKB2n4yWpbSsVXYDalHAHveHwsxVJzOw 4ecLB1tR9TadjtFpclLg/ODXAqhT94vno709FHTPQ7ZbSRNFTsT7nUAM5J+bycANV7eG aLGP9MoMcl162VqmFiIRtbyomu5EM+7h8w76o5lWRUl1+Fdufx8A1AMssYupXyOd3WY/ 17Pg== X-Gm-Message-State: AMCzsaVgZ1NW+EldvQw3x8saUHfAIJL8Oai5n3JSVbMDikvqk9aDB4Q3 uzC0gP/FXvzPtanwFMuqAHFckA== X-Google-Smtp-Source: ABhQp+QiPexV4SAPkczPyAPXJ1vtewPi5wUphT5atchTrqYRiGBf7cSU1aBO7FZ330VoeXORvpJtsg== X-Received: by 10.28.206.142 with SMTP id e136mr3809946wmg.27.1509508460179; Tue, 31 Oct 2017 20:54:20 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f27sm8282731wrf.63.2017.10.31.20.54.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 31 Oct 2017 20:54:18 -0700 (PDT) Date: Wed, 1 Nov 2017 03:54:17 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171101035417.tvidg4hioeue4ecu@bivouac.eciton.net> References: <1509422375-20198-1-git-send-email-mw@semihalf.com> <1509422375-20198-7-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1509422375-20198-7-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Nov 2017 03:50:29 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Oct 31, 2017 at 04:59:35AM +0100, Marcin Wojtas wrote: > In the MvSpiDxe driver obtaining host register base address, > controller clock and device maximum frequency directly from PCDs > was done all over the code. This patch cleans up the parameters' > handling and enables accessing them from SPI_DEVICE structure fields. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 ++++++++++++-------- > Platform/Marvell/Include/Protocol/Spi.h | 2 + > 2 files changed, 31 insertions(+), 19 deletions(-) > > diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > index a7db5f2..c60a520 100755 > --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance; > STATIC > EFI_STATUS > SpiSetBaudRate ( > + IN SPI_DEVICE *Slave, > IN UINT32 CpuClock, > IN UINT32 MaxFreq > ) > { > UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff; > - UINTN SpiRegBase = PcdGet32 (PcdSpiRegBase); > + UINTN SpiRegBase = Slave->HostRegisterBaseAddress; > > MinBaudDiff = 0xFFFFFFFF; > BestSppr = 0; > @@ -93,26 +94,28 @@ SpiSetBaudRate ( > STATIC > VOID > SpiSetCs ( > - UINT8 CsId > + IN SPI_DEVICE *Slave > ) > { > - UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); > + UINT32 Reg; > + UINTN SpiRegBase = Slave->HostRegisterBaseAddress; > > Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); > Reg &= ~SPI_CS_NUM_MASK; > - Reg |= (CsId << SPI_CS_NUM_OFFSET); > + Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET); > MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); > } > > STATIC > VOID > SpiActivateCs ( > - UINT8 IN CsId > + IN SPI_DEVICE *Slave > ) > { > - UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); > + UINT32 Reg; > + UINTN SpiRegBase = Slave->HostRegisterBaseAddress; > > - SpiSetCs(CsId); > + SpiSetCs(Slave); > Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); > Reg |= SPI_CS_EN_MASK; > MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); > @@ -121,10 +124,11 @@ SpiActivateCs ( > STATIC > VOID > SpiDeactivateCs ( > - VOID > + IN SPI_DEVICE *Slave > ) > { > - UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); > + UINT32 Reg; > + UINTN SpiRegBase = Slave->HostRegisterBaseAddress; > > Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); > Reg &= ~SPI_CS_EN_MASK; > @@ -139,14 +143,15 @@ SpiSetupTransfer ( > ) > { > SPI_MASTER *SpiMaster; > - UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; > + UINT32 Reg, CoreClock, SpiMaxFreq; > + UINTN SpiRegBase; > > SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); > > // Initialize values from PCDs > - SpiRegBase = PcdGet32 (PcdSpiRegBase); > - CoreClock = PcdGet32 (PcdSpiClockFrequency); > - SpiMaxFreq = PcdGet32 (PcdSpiMaxFrequency); > + SpiRegBase = Slave->HostRegisterBaseAddress; > + CoreClock = Slave->CoreClock; > + SpiMaxFreq = Slave->MaxFreq; > > EfiAcquireLock (&SpiMaster->Lock); > > @@ -154,9 +159,9 @@ SpiSetupTransfer ( > Reg |= SPI_BYTE_LENGTH; > MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); > > - SpiSetCs(Slave->Cs); > + SpiSetCs(Slave); > > - SpiSetBaudRate (CoreClock, SpiMaxFreq); > + SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq); > > Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); > Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK); > @@ -194,21 +199,22 @@ MvSpiTransfer ( > { > SPI_MASTER *SpiMaster; > UINT64 Length; > - UINT32 Iterator, Reg, SpiRegBase; > + UINT32 Iterator, Reg; > UINT8 *DataOutPtr = (UINT8 *)DataOut; > UINT8 *DataInPtr = (UINT8 *)DataIn; > UINT8 DataToSend = 0; > + UINTN SpiRegBase; > > SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); > > - SpiRegBase = PcdGet32 (PcdSpiRegBase); > + SpiRegBase = Slave->HostRegisterBaseAddress; > > Length = 8 * DataByteCount; > > EfiAcquireLock (&SpiMaster->Lock); > > if (Flag & SPI_TRANSFER_BEGIN) { > - SpiActivateCs (Slave->Cs); > + SpiActivateCs (Slave); > } > > // Set 8-bit mode > @@ -245,7 +251,7 @@ MvSpiTransfer ( > } > > if (Flag & SPI_TRANSFER_END) { > - SpiDeactivateCs (); > + SpiDeactivateCs (Slave); > } > > EfiReleaseLock (&SpiMaster->Lock); > @@ -312,6 +318,10 @@ MvSpiSetupSlave ( > Slave->Mode = Mode; > } > > + Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase); > + Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency); > + Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency); > + > SpiSetupTransfer (This, Slave); > > return Slave; > diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Include/Protocol/Spi.h > index 0cf7914..b8981f3 100644 > --- a/Platform/Marvell/Include/Protocol/Spi.h > +++ b/Platform/Marvell/Include/Protocol/Spi.h > @@ -52,6 +52,8 @@ typedef struct { > INTN MaxFreq; > SPI_MODE Mode; > NOR_FLASH_INFO *Info; > + UINTN HostRegisterBaseAddress; > + UINTN CoreClock; > } SPI_DEVICE; > > typedef > -- > 2.7.4 >