From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 667BA20945BDC for ; Tue, 31 Oct 2017 21:45:39 -0700 (PDT) Received: by mail-wr0-x242.google.com with SMTP id w105so932657wrc.0 for ; Tue, 31 Oct 2017 21:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=zP3qvRqmxIoO6u9BBRutGHwB0mjvF/FfGqRdX2I0h0k=; b=V0sRnl1I55kzlD2GzbjUsDUNmOADOsdhYJjq6l6AYVg9weH5rZAl1Vnbeh1b/nG46l XGyA93kUQYJGfZA0erJhtBUcboYntGGdNaVXsKwo+bThdKgPB69O/GrmiAJ+lkGFyRtC ppPRBc0CdJyQ23t98Gd/QeODuDOCrJbiFPUDk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=zP3qvRqmxIoO6u9BBRutGHwB0mjvF/FfGqRdX2I0h0k=; b=AuChPyEKC/Nh4N/5abg2xtAHQW+j4T14pMeKpzAGzG0USNDbyLTYnJV7s4XmAIVZ8y goL8rRuOlhmLC6rmN5UmZkBrCVdDmRRpf/39Y6d/XClwaDzvus4/yneyVvistRy1O+1S a8BpNgd6ICGKa5NQzqiW6H9Pw0qVs1jHc/P4gDm19H5H+a8AWacbkbNgsrvhsOQFIgu0 awFlYzHtw+T6WCdbRwoFquCJ0RyEaEJAoJuA5yYBG4LPm5+3iY6x8cHKh6WmV1p6NMLF 4ytklYVAPkUXCy7UJ44xs4qbLtY642wCTNwRaKHlNaOVEjr3O04jzMFrK7cDiGtQiu5u aqSA== X-Gm-Message-State: AMCzsaXZTLFxEan4ztCgHD3XTE8tLNulzw2AtBCcTG8+cr872fHgq3kl WTZSL4arfOyQGyXqdyPXQVTN7YNioKI= X-Google-Smtp-Source: ABhQp+ReoqCgCLwVUIRXdD/kHGo0r9xQF1AXIQMCnABwdY8E3Iy33SSBJtkbJYqKjzLQJTyLOLFO8A== X-Received: by 10.223.154.74 with SMTP id z68mr3593833wrb.36.1509511770453; Tue, 31 Oct 2017 21:49:30 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j2sm2713855wrj.82.2017.10.31.21.49.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 31 Oct 2017 21:49:29 -0700 (PDT) Date: Wed, 1 Nov 2017 04:49:28 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, graeme.gregory@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com Message-ID: <20171101044928.4oikrmlbmrwwjdyv@bivouac.eciton.net> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> <20171031105218.30208-6-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171031105218.30208-6-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v3 05/27] Silicon/SynQuacer: add MemoryInitPeiLib implementation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Nov 2017 04:45:39 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Oct 31, 2017 at 10:51:56AM +0000, Ard Biesheuvel wrote: > Implement MemoryInitPeiLib based on the newly added DramInfo > PPI, which retrieves the DRAM information from lower level > firmware. > > Note that the firmware volumes in SPI NOR are mapped with > different attributes: the FV containing the PEI modules that > may execute in place is mapped as uncached memory, given that > it requires executable permissions. The FV containing the > compressed DXE modules is mapped with device attributes for > performance (!), and copied into DRAM by the platform PEIM > once permanent memory is installed. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 186 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 67 +++++++ > 2 files changed, 253 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > new file mode 100644 > index 000000000000..e9a266f0997a > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > @@ -0,0 +1,186 @@ > +/** @file > +* > +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. > +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#include > + > +#define ARM_MEMORY_REGION(Base, Size) \ > + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK } > + > +#define ARM_UNCACHED_REGION(Base, Size) \ > + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED } > + > +#define ARM_DEVICE_REGION(Base, Size) \ > + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE } > + > +VOID > +BuildMemoryTypeInformationHob ( > + VOID > + ); > + > +STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes = > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED; > + > +STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { > + // Memory mapped SPI NOR flash > + // Mapped with device attributes for performance (!) > + ARM_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress), > + FixedPcdGet32 (PcdFdSize)), > + > + // Memory mapped SPI NOR flash - XIP region > + // Sub-region of the preceding one - supersede with normal-nc attributes > + ARM_UNCACHED_REGION (FixedPcdGet64 (PcdFvBaseAddress), > + FixedPcdGet32 (PcdFvSize)), > + > + // SynQuacer OnChip peripherals > + ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, > + SYNQUACER_PERIPHERALS_SZ), > + > + // SynQuacer OnChip non-secure SRAM > + ARM_UNCACHED_REGION (SYNQUACER_NON_SECURE_SRAM_BASE, > + SYNQUACER_NON_SECURE_SRAM_SZ), > + > + // SynQuacer GIC-500 > + ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE), > + ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE), > + > + // SynQuacer eMMC(SDH30) > + ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ), > + > + // SynQuacer EEPROM - could point to NOR flash as well > + ARM_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase), > + SYNQUACER_EEPROM_BASE_SZ), > + > + // SynQuacer NETSEC > + ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ), > + > + // PCIe control registers > + ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE), > + > + // PCIe config space > + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE, > + SYNQUACER_PCI_SEG0_CONFIG_SIZE), > + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE, > + SYNQUACER_PCI_SEG1_CONFIG_SIZE), > + > + // PCIe I/O space > + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, > + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE), > + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, > + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE), > +}; > + > +STATIC > +EFI_STATUS > +DeclareDram ( > + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryTable > + ) > +{ > + SYNQUACER_DRAM_INFO_PPI *DramInfo; > + EFI_STATUS Status; > + UINTN Idx; > + UINTN RegionCount; > + UINT64 Base; > + UINT64 Size; > + ARM_MEMORY_REGION_DESCRIPTOR *DramDescriptor; > + > + Status = PeiServicesLocatePpi (&gSynQuacerDramInfoPpiGuid, 0, NULL, > + (VOID **)&DramInfo); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Status = DramInfo->GetRegionCount (&RegionCount); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + *VirtualMemoryTable = AllocatePool (sizeof (mVirtualMemoryTable) + > + (RegionCount + 1) * > + sizeof (ARM_MEMORY_REGION_DESCRIPTOR)); > + if (*VirtualMemoryTable == NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + CopyMem (*VirtualMemoryTable, mVirtualMemoryTable, > + sizeof (mVirtualMemoryTable)); > + > + DramDescriptor = *VirtualMemoryTable + ARRAY_SIZE (mVirtualMemoryTable); > + > + for (Idx = 0; Idx < RegionCount; Idx++, DramDescriptor++) { > + Status = DramInfo->GetRegion (Idx, &Base, &Size); > + ASSERT_EFI_ERROR (Status); > + > + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, > + mDramResourceAttributes, Base, Size); > + > + DramDescriptor->PhysicalBase = Base; > + DramDescriptor->VirtualBase = Base; > + DramDescriptor->Length = Size; > + DramDescriptor->Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + } > + > + DramDescriptor->PhysicalBase = 0; > + DramDescriptor->VirtualBase = 0; > + DramDescriptor->Length = 0; > + DramDescriptor->Attributes = 0; > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +MemoryPeim ( > + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, > + IN UINT64 UefiMemorySize > + ) > +{ > + EFI_STATUS Status; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + > + Status = DeclareDram (&VirtualMemoryTable); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Status = ArmConfigureMmu (VirtualMemoryTable, NULL, NULL); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { > + // Optional feature that helps prevent EFI memory map fragmentation. > + BuildMemoryTypeInformationHob (); > + } > + return EFI_SUCCESS; > +} > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf > new file mode 100644 > index 000000000000..06cad772a1c0 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf > @@ -0,0 +1,67 @@ > +#/** @file > +# > +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x00010019 > + BASE_NAME = SynQuacerMemoryInitPeiLib > + FILE_GUID = c69d3ce7-098c-4fcd-afb4-15fb05a39308 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM > + > +[Sources] > + SynQuacerMemoryInitPeiLib.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Socionext/SynQuacer/SynQuacer.dec > + > +[LibraryClasses] > + ArmLib > + ArmMmuLib > + BaseMemoryLib > + DebugLib > + MemoryAllocationLib > + PeiServicesLib > + > +[FeaturePcd] > + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFdSize > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdFvSize > + gArmTokenSpaceGuid.PcdGicDistributorBase > + gArmTokenSpaceGuid.PcdGicRedistributorsBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase > + > +[Pcd] > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + > +[Ppis] > + gSynQuacerDramInfoPpiGuid ## CONSUMES > + > +[Depex] > + gSynQuacerDramInfoPpiGuid > -- > 2.11.0 >