From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::229; helo=mail-wm0-x229.google.com; envelope-from=graeme.gregory@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 47C9121C913DF for ; Wed, 1 Nov 2017 03:13:05 -0700 (PDT) Received: by mail-wm0-x229.google.com with SMTP id n74so15963761wmi.1 for ; Wed, 01 Nov 2017 03:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=iJFyxweu6M3yuv7cdJeYSkUKRu+JLsUzEG4aA6ISHAw=; b=cBtr8RzC38W5s5zcCu9H5Gqyj60CfrqetRjqxEXQ2ZptXoH1dxSLcj+2NnWkbbkY7t jmOTWyLm18Y27HlfGjiQKbMle37SaaoBRWrg+S2fwRqQiJu/CdyA0oLHRWYjyylQGKxR W+/jia8c+7d9J/3cO3C9wisg+N5U8qba9lL5M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=iJFyxweu6M3yuv7cdJeYSkUKRu+JLsUzEG4aA6ISHAw=; b=RS0ZgzgEM+IvEA9JzONDMHPfTXqGDhIxXTbt8NYqzgW60Pj+7ZDrAfzvG00VEGRuwa Hb4B1PAYzBhYrX8jyCBcV8WFgmlhKE5MLdF21yz8MAtPBrLHR/W0L/ebCc16l19PAOnB ivZTYj05cfYvHPaa6FFyQTRD8TkFqRCnquRHIZJDDQGCqZAM6kzdEeyLpTrAUrbomZxK /XbAlFxwZweIgscf7YQ89JEUjZA1oOrHsvDuetZ0gU4E4rHqqWSeApX9DRPm7oQtDw9u 7IOBPa2CTo4yKpICnnIYvFwxmfaSl7b2VFSLTM8TgVO2tpUP6N0YHe3fxfogvmUJ2uCN RSlg== X-Gm-Message-State: AMCzsaU3UPMEwPwZAclZ8UqK2UN2OUcLzpTqgGYe4/1JCsQjLkOkcgQs r6EsWNxZaRlP9kC6mYMMw1VyRfeLI0U= X-Google-Smtp-Source: ABhQp+Ql5nx+NrLUhkeC/rkiNIOhktNx/kMzJOHDuOfewM0hh0PKZTxaMsw9khcG+ivo3W2sEZV9/A== X-Received: by 10.28.32.216 with SMTP id g207mr3871362wmg.138.1509531416104; Wed, 01 Nov 2017 03:16:56 -0700 (PDT) Received: from localhost (host-92-20-153-227.as13285.net. [92.20.153.227]) by smtp.gmail.com with ESMTPSA id v35sm737982wrc.13.2017.11.01.03.16.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 01 Nov 2017 03:16:55 -0700 (PDT) Date: Wed, 1 Nov 2017 10:15:57 +0000 From: graeme.gregory@linaro.org To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com Message-ID: <20171101101557.GA25801@linaro-xps13-gg.xora.org.uk> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> <20171031105218.30208-13-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171031105218.30208-13-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.9.1 (2017-09-22) Subject: Re: [PATCH edk2-platforms v3 12/27] Silicon/SynQuacer: add ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Nov 2017 10:13:07 -0000 X-Groupsio-MsgNum: 16840 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="u3/rZRmxL6MmkK24" Content-Disposition: inline --u3/rZRmxL6MmkK24 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable I see nothing wrong with the ACPI in this patch, but I question the sanity of exposing ACPI on this SoC where it seems to be not suited. Given the comment in the commit message would an alternative OS like windows actually work with this PCIe setup? Graeme On Tue, Oct 31, 2017 at 10:52:03AM +0000, Ard Biesheuvel wrote: > Enable ACPI support for the SynQuacerEvalBoard platform: add descriptions > of the CPUs, the GIC, the serial port, the timers and the PCIe RCs, > including the MSI routing via the GICv3 ITS. >=20 > Note that PCIe support is limited to a single bus per RC. Anything beyond > that is unsupported due to a limitation in the hardware that makes it > impossible to expose the PCIe RCs in a fully ECAM compliant manner. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 15 + > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 14 + > Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 294 +++++= +++++++++++++++ > Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 58 ++++ > Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 62 +++++ > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 167 +++++= ++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 89 ++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 98 +++++= ++ > Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 164 +++++= ++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 152 +++++= +++++ > Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 +++++ > Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 127 +++++= ++++ > 12 files changed, 1303 insertions(+) >=20 > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc= b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > index f8579e5739b5..02db912562bd 100644 > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > @@ -529,3 +529,18 @@ [Components.common] > > DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf > } > + > + # > + # ACPI support > + # > + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { > + > + #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf > + > + > + # support ACPI v5.0 or later > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 > + } > + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > + Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsR= esourceTableDxe.inf > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf= b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf > index 3e1af577371a..2935f19139b6 100644 > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf > @@ -198,6 +198,14 @@ [FV.FvMain] > INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf > INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf > =20 > + # > + # ACPI support > + # > + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > + INF RuleOverride =3D ACPITABLE Silicon/Socionext/SynQuacer/AcpiTables/= AcpiTables.inf > + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraph= icsResourceTableDxe.inf > + > [FV.FVMAIN_PEI] > FvAlignment =3D 16 > ERASE_POLARITY =3D 1 > @@ -354,3 +362,9 @@ [Rule.Common.UEFI_APPLICATION.BINARY] > UI STRING=3D"$(MODULE_NAME)" Optional > VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUM= BER) > } > + > +[Rule.Common.USER_DEFINED.ACPITABLE] > + FILE FREEFORM =3D $(NAMED_GUID) { > + RAW ACPI |.acpi > + RAW ASL |.aml > + } > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b= /Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > new file mode 100644 > index 000000000000..fb845d2c107e > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > @@ -0,0 +1,294 @@ > +/** @file > + Secondary System Description Table (SSDT) for SynQuacer PCIe RCs > + > + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the = BSD License > + which accompanies this distribution. The full text of the license may= be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > + > +**/ > + > +#include > + > +#include "AcpiTables.h" > + > +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", EFI_ACPI_OE= M_REVISION) > +{ > + Scope(_SB) > + { > + // > + // PCI Root Complex > + // > + Device(PCI0) > + { > + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge > + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge > + Name(_SEG, Zero) // PCI Segment Group number > + Name(_BBN, Zero) // PCI Base Bus Number > + Name(_CCA, 1) // Cache Coherency Attribute > + > + // PCI Routing Table > + Name(_PRT, Package() { > + Package () { 0xFFFF, 0, Zero, 222 }, // INTA > + Package () { 0xFFFF, 1, Zero, 222 }, // INTB > + Package () { 0xFFFF, 2, Zero, 222 }, // INTC > + Package () { 0xFFFF, 3, Zero, 222 }, // INTD > + }) > + // Root complex resources > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( // Bus numbers assigned to this root > + ResourceProducer, > + MinFixed, MaxFixed, PosDecode, > + 0, // AddressGranularity > + SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMinimum - = Minimum Bus Number > + SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMaximum - = Maximum Bus Number > + 0, // AddressTranslatio= n - Set to 0 > + 1 // RangeLength - Num= ber of Busses > + ) > + > + DWordMemory ( // 32-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Addr= ess > + 0x00000000, // Translate > + SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length > + ) > + > + QWordMemory ( // 64-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Addr= ess > + 0x00000000, // Translate > + SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length > + ) > + > + DWordIo ( // IO window > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + EntireRange, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Addr= ess > + SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate > + SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length > + , > + , > + , > + TypeTranslation > + ) > + }) // Name(RBUF) > + > + Return (RBUF) > + } // Method(_CRS) > + > + Device (RES0) > + { > + Name (_HID, "PNP0C02") > + Name (_CRS, ResourceTemplate () > + { > + Memory32Fixed (ReadWrite, > + SYNQUACER_PCI_SEG0_CONFIG_BASE, > + SYNQUACER_PCI_SEG0_CONFIG_SIZE) > + }) > + } > + > + // > + // OS Control Handoff > + // > + Name(SUPP, Zero) // PCI _OSC Support Field value > + Name(CTRL, Zero) // PCI _OSC Control Field value > + > + /* > + See [1] 6.2.10, [2] 4.5 > + */ > + Method(_OSC,4) { > + // Check for proper UUID > + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"= ))) { > + // Create DWord-adressable fields from the Capabilities = Buffer > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + CreateDWordField(Arg3,8,CDW3) > + > + // Save Capabilities DWord2 & 3 > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // Only allow native hot plug control if OS supports: > + // * ASPM > + // * Clock PM > + // * MSI/MSI-X > + If(LNotEqual(And(SUPP, 0x16), 0x16)) { > + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bit= s) > + } > + > + // Always allow native PME, AER (no dependencies) > + > + // Never allow SHPC (no SHPC controller in this system) > + And(CTRL,0x1D,CTRL) > + > + If(LNotEqual(Arg1,One)) { // Unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were = masked > + Or(CDW1,0x10,CDW1) > + } > + // Update DWORD3 in the buffer > + Store(CTRL,CDW3) > + Return(Arg3) > + } Else { > + Or(CDW1,4,CDW1) // Unrecognized UUID > + Return(Arg3) > + } > + } // End _OSC > + } // PCI0 > + > + Device(PCI1) > + { > + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge > + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge > + Name(_SEG, 1) // PCI Segment Group number > + Name(_BBN, Zero) // PCI Base Bus Number > + Name(_CCA, 1) // Cache Coherency Attribute > + > + // PCI Routing Table > + Name(_PRT, Package() { > + Package () { 0xFFFF, 0, Zero, 214 }, // INTA > + Package () { 0xFFFF, 1, Zero, 214 }, // INTB > + Package () { 0xFFFF, 2, Zero, 214 }, // INTC > + Package () { 0xFFFF, 3, Zero, 214 }, // INTD > + }) > + // Root complex resources > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( // Bus numbers assigned to this root > + ResourceProducer, > + MinFixed, MaxFixed, PosDecode, > + 0, // AddressGranularity > + SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMinimum - = Minimum Bus Number > + SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMaximum - = Maximum Bus Number > + 0, // AddressTranslatio= n - Set to 0 > + 1 // RangeLength - Num= ber of Busses > + ) > + > + DWordMemory ( // 32-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Addr= ess > + 0x00000000, // Translate > + SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length > + ) > + > + QWordMemory ( // 64-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG1_MMIO64_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG1_MMIO64_MAX, // Max Base Addr= ess > + 0x00000000, // Translate > + SYNQUACER_PCI_SEG1_MMIO64_SIZE // Length > + ) > + > + DWordIo ( // IO window > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + EntireRange, > + 0x00000000, // Granularity > + SYNQUACER_PCI_SEG1_PORTIO_MIN, // Min Base Addr= ess > + SYNQUACER_PCI_SEG1_PORTIO_MAX, // Max Base Addr= ess > + SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, // Translate > + SYNQUACER_PCI_SEG1_PORTIO_SIZE, // Length > + , > + , > + , > + TypeTranslation > + ) > + }) // Name(RBUF) > + > + Return (RBUF) > + } // Method(_CRS) > + > + Device (RES0) > + { > + Name (_HID, "PNP0C02") > + Name (_CRS, ResourceTemplate () > + { > + Memory32Fixed (ReadWrite, > + SYNQUACER_PCI_SEG1_CONFIG_BASE, > + SYNQUACER_PCI_SEG1_CONFIG_SIZE) > + }) > + } > + > + // > + // OS Control Handoff > + // > + Name(SUPP, Zero) // PCI _OSC Support Field value > + Name(CTRL, Zero) // PCI _OSC Control Field value > + > + /* > + See [1] 6.2.10, [2] 4.5 > + */ > + Method(_OSC,4) { > + // Check for proper UUID > + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"= ))) { > + // Create DWord-adressable fields from the Capabilities = Buffer > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + CreateDWordField(Arg3,8,CDW3) > + > + // Save Capabilities DWord2 & 3 > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // Only allow native hot plug control if OS supports: > + // * ASPM > + // * Clock PM > + // * MSI/MSI-X > + If(LNotEqual(And(SUPP, 0x16), 0x16)) { > + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bit= s) > + } > + > + // Always allow native PME, AER (no dependencies) > + > + // Never allow SHPC (no SHPC controller in this system) > + And(CTRL,0x1D,CTRL) > + > + If(LNotEqual(Arg1,One)) { // Unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were = masked > + Or(CDW1,0x10,CDW1) > + } > + // Update DWORD3 in the buffer > + Store(CTRL,CDW3) > + Return(Arg3) > + } Else { > + Or(CDW1,4,CDW1) // Unrecognized UUID > + Return(Arg3) > + } > + } // End _OSC > + } // PCI0 > + } > +} > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h b/Silico= n/Socionext/SynQuacer/AcpiTables/AcpiTables.h > new file mode 100644 > index 000000000000..f75719b15186 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h > @@ -0,0 +1,58 @@ > +/** @file > +* > +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. > +* Copyright (c) 2017, Linaro Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the= BSD License > +* which accompanies this distribution. The full text of the license ma= y be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +* > +**/ > + > +#ifndef __ACPITABLES_H__ > +#define __ACPITABLES_H__ > + > +// > +// ACPI table information used to initialize tables. > +// > +#define EFI_ACPI_OEM_ID 'S','N','I',' ',' ',' ' // OEMID 6 b= ytes long > +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('S','Y','N','Q','U','A','= C','R') // OEM table id 8 bytes long > +#define EFI_ACPI_OEM_REVISION 0x20170913 > +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') > +#define EFI_ACPI_CREATOR_REVISION 0x00000001 > + > +// A macro to initialise the common header part of EFI ACPI tables as de= fined by > +// EFI_ACPI_DESCRIPTION_HEADER structure. > +#define __ACPI_HEADER(Signature, Type, Revision) { \ > + Signature, /* UINT32 Signature */ \ > + sizeof (Type), /* UINT32 Length */ \ > + Revision, /* UINT8 Revision */ \ > + 0, /* UINT8 Checksum */ \ > + { EFI_ACPI_OEM_ID }, /* UINT8 OemId[6] */ \ > + EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ > + EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ > + EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ > + EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ > + } > + > +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLe= ngth) \ > + { \ > + EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisReg= ionAddr, RedisDiscLength \ > + } > + > +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \ > + { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id,= PhysAddress, 0 } > + > +#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePh= ysicalAddress, \ > + ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags) = \ > + { = \ > + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SB= SA_GENERIC_WATCHDOG_STRUCTURE), \ > + EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhy= sicalAddress, \ > + WatchdogTimerGSIV, WatchdogTimerFlags = \ > + } > + > +#endif > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Sili= con/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > new file mode 100644 > index 000000000000..82911285da21 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > @@ -0,0 +1,62 @@ > +## @file > +# > +# ACPI table data and ASL sources required to boot the platform. > +# > +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. > +# Copyright (c) 2017, Linaro Ltd. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the= BSD License > +# which accompanies this distribution. The full text of the license ma= y be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x0001001A > + BASE_NAME =3D SynQuacerAcpiTables > + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD > + MODULE_TYPE =3D USER_DEFINED > + VERSION_STRING =3D 1.0 > + > +[Sources] > + AcpiTables.h > + AcpiSsdtRootPci.asl > + Dsdt.asl > + Fadt.aslc > + Gtdt.aslc > + Iort.aslc > + Madt.aslc > + Mcfg.aslc > + Spcr.aslc > + > +[Packages] > + ArmPlatformPkg/ArmPlatformPkg.dec > + ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec > + Silicon/Socionext/SynQuacer/SynQuacer.dec > + > +[FixedPcd] > + gArmPlatformTokenSpaceGuid.PcdClusterCount > + gArmPlatformTokenSpaceGuid.PcdCoreCount > + gArmTokenSpaceGuid.PcdGicDistributorBase > + gArmTokenSpaceGuid.PcdGicRedistributorsBase > + > + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum > + > + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase > + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > + > + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase > + gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/So= cionext/SynQuacer/AcpiTables/Dsdt.asl > new file mode 100644 > index 000000000000..d71020f84eac > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -0,0 +1,167 @@ > +/** @file > + Differentiated System Description Table Fields (DSDT) > + > + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the = BSD License > + which accompanies this distribution. The full text of the license may= be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > + > +**/ > + > +#include "AcpiTables.h" > + > +#include > + > +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", EFI_ACPI_= OEM_REVISION) { > + Scope(_SB) { > + // > + // A53x4 Processor declaration > + // > + Device(CP00) { // A53-0: Cluster 0, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 0) > + } > + Device(CP01) { // A53-0: Cluster 0, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 1) > + } > + > + Device(CP04) { // A53-0: Cluster 1, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 2) > + } > + Device(CP05) { // A53-0: Cluster 1, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 3) > + } > + > + Device(CP08) { // A53-0: Cluster 2, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 4) > + } > + Device(CP09) { // A53-0: Cluster 2, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 5) > + } > + > + Device(CP12) { // A53-0: Cluster 3, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 6) > + } > + Device(CP13) { // A53-0: Cluster 3, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 7) > + } > + > + Device(CP16) { // A53-0: Cluster 4, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 8) > + } > + Device(CP17) { // A53-0: Cluster 4, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 9) > + } > + > + Device(CP20) { // A53-0: Cluster 5, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 10) > + } > + Device(CP21) { // A53-0: Cluster 5, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 11) > + } > + > + Device(CP24) { // A53-0: Cluster 6, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 12) > + } > + Device(CP25) { // A53-0: Cluster 6, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 13) > + } > + > + Device(CP28) { // A53-0: Cluster 7, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 14) > + } > + Device(CP29) { // A53-0: Cluster 7, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 15) > + } > + > + Device(CP32) { // A53-0: Cluster 8, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 16) > + } > + Device(CP33) { // A53-0: Cluster 8, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 17) > + } > + > + Device(CP36) { // A53-0: Cluster 9, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 18) > + } > + Device(CP37) { // A53-0: Cluster 9, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 19) > + } > + > + Device(CP40) { // A53-0: Cluster 10, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 20) > + } > + Device(CP41) { // A53-0: Cluster 10, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 21) > + } > + > + Device(CP44) { // A53-0: Cluster 11, Cpu 0 > + Name(_HID, "ACPI0007") > + Name(_UID, 22) > + } > + Device(CP45) { // A53-0: Cluster 11, Cpu 1 > + Name(_HID, "ACPI0007") > + Name(_UID, 23) > + } > + > + // UART PL011 > + Device(COM0) { > + Name(_HID, "ARMH0011") > + Name(_CID, "PL011") > + Name(_UID, Zero) > + Name(_CRS, ResourceTemplate() { > + Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), = 0x1000) > + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } > + }) > + } > + > + Device(NET0) { > + Name(_HID, "SCX0001") > + Name(_UID, Zero) > + Name(_CCA, Zero) > + Name(_CRS, ResourceTemplate() { > + Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE, > + SYNQUACER_NETSEC_BASE_SZ) > + Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdNetsecEepromBase), 0x= 10000) > + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 } > + }) > + > + Name (_DSD, Package () // _DSD: Device-Specific Data > + { > + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () { > + Package (2) { "phy-mode", "rgmii" }, > + Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddres= s) }, > + Package (2) { "max-speed", 1000 }, > + Package (2) { "max-frame-size", 9000 }, > + Package (2) { "socionext,phy-clock-frequency", 125000000 }, > + } > + }) > + } > + } // Scope(_SB) > +} > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Fadt.aslc > new file mode 100644 > index 000000000000..358ed67c2f16 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc > @@ -0,0 +1,89 @@ > +/** @file > +* Fixed ACPI Description Table (FADT) > +* > +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the= BSD License > +* which accompanies this distribution. The full text of the license ma= y be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +* > +**/ > + > +#include > +#include > + > +#include "AcpiTables.h" > + > +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { > + __ACPI_HEADER ( > + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, > + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION > + ), > + 0, // UINT32 = FirmwareCtrl > + 0, // UINT32 = Dsdt > + EFI_ACPI_RESERVED_BYTE, // UINT8 = Reserved0 > + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 = PreferredPmProfile > + 0, // UINT16 = SciInt > + 0, // UINT32 = SmiCmd > + 0, // UINT8 = AcpiEnable > + 0, // UINT8 = AcpiDisable > + 0, // UINT8 = S4BiosReq > + 0, // UINT8 = PstateCnt > + 0, // UINT32 = Pm1aEvtBlk > + 0, // UINT32 = Pm1bEvtBlk > + 0, // UINT32 = Pm1aCntBlk > + 0, // UINT32 = Pm1bCntBlk > + 0, // UINT32 = Pm2CntBlk > + 0, // UINT32 = PmTmrBlk > + 0, // UINT32 = Gpe0Blk > + 0, // UINT32 = Gpe1Blk > + 0, // UINT8 = Pm1EvtLen > + 0, // UINT8 = Pm1CntLen > + 0, // UINT8 = Pm2CntLen > + 0, // UINT8 = PmTmrLen > + 0, // UINT8 = Gpe0BlkLen > + 0, // UINT8 = Gpe1BlkLen > + 0, // UINT8 = Gpe1Base > + 0, // UINT8 = CstCnt > + 0, // UINT16 = PLvl2Lat > + 0, // UINT16 = PLvl3Lat > + 0, // UINT16 = FlushSize > + 0, // UINT16 = FlushStride > + 0, // UINT8 = DutyOffset > + 0, // UINT8 = DutyWidth > + 0, // UINT8 = DayAlrm > + 0, // UINT8 = MonAlrm > + 0, // UINT8 = Century > + 0, // UINT16 = IaPcBootArch > + 0, // UINT8 = Reserved1 > + EFI_ACPI_6_0_HW_REDUCED_ACPI | > + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 = Flags > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE ResetReg > + 0, // UINT8 = ResetValue > + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 = ArmBootArchFlags > + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorRevision > + 0, // UINT64 = XFirmwareCtrl > + 0, // UINT64 = XDsdt > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg > + NULL_GAS, // EFI_ACPI_= 6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg > + 0 // UINT64 = HypervisorVendorIdentity; > +}; > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving the > +// data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Fadt; > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Gtdt.aslc > new file mode 100644 > index 000000000000..f22c27f05454 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc > @@ -0,0 +1,98 @@ > +/** @file > +* Generic Timer Description Table (GTDT) > +* > +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. > +* Copyright (c) 2017, Linaro Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the= BSD License > +* which accompanies this distribution. The full text of the license ma= y be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > + > +#include "AcpiTables.h" > + > +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMO= RY_MAPPED_BLOCK_PRESENT > +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 > +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTE= RRUPT_MODE > +#define GTDT_GLOBAL_FLAGS_LEVEL 0 > + > +#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GT= DT_GLOBAL_FLAGS_LEVEL) > +#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF > + > +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_I= NTERRUPT_MODE > +#define GTDT_TIMER_LEVEL_TRIGGERED 0 > +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_I= NTERRUPT_POLARITY > +#define GTDT_TIMER_ACTIVE_HIGH 0 > + > +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_= LEVEL_TRIGGERED) > + > +#pragma pack (1) > + > +typedef struct { > + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; > + EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE TimerBase; > + EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE TimerFrame; > + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdog; > +} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES; > + > +#pragma pack () > + > +EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt =3D { > + { > + __ACPI_HEADER( > + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES, > + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION > + ), > + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAdd= ress > + 0, // UINT32 Reserved > + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Ti= merGSIV > + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Ti= merFlags > + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL= 1TimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 1TimerFlags > + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV > + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags > + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL= 2TimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 2TimerFlags > + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= PhysicalAddress > + 2, // UINT32 PlatformTim= erCount > + sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 Plat= =66romTimerOffset > + }, > + { > + EFI_ACPI_6_0_GTDT_GT_BLOCK, // UINT8= Type > + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) + > + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE), // UINT1= 6 Length > + EFI_ACPI_RESERVED_BYTE, // UINT8= Reserved > + 0x2A810000, // UINT6= 4 CntCtlBase > + 1, // UINT3= 2 GTBlockTimerCount > + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) // UINT3= 2 GTBlockTimerOffset > + }, > + { > + 0, // UINT8= GTFrameNumber > + {0, 0, 0}, // UINT8= Reserved[3] > + 0x2A830000, // UINT6= 4 CntBaseX > + 0xFFFFFFFFFFFFFFFF, // UINT6= 4 CntEL0BaseX > + 92, // UINT3= 2 GTxPhysicalTimerGSIV > + GTDT_TIMER_LEVEL_TRIGGERED | GTDT_TIMER_ACTIVE_HIGH, // UINT3= 2 GTxPhysicalTimerFlags > + 0, // UINT3= 2 GTxVirtualTimerGSIV > + 0, // UINT3= 2 GTxVirtualTimerFlags > + EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY // UINT3= 2 GTxCommonFlags > + }, > + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( > + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGen= ericWatchdogControlBase), 94, 0), > +}; > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving the > +// data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Gtdt; > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Iort.aslc > new file mode 100644 > index 000000000000..bbb425f1f808 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc > @@ -0,0 +1,164 @@ > +/** @file > + > + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the = BSD License > + which accompanies this distribution. The full text of the license may= be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > + > +**/ > + > +#include > + > +#include "AcpiTables.h" > + > +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, nam= e) > + > +#pragma pack(1) > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; > + UINT32 Identifiers[1]; > +} SYNQUACER_ITS_NODE; > + > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; > + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[2]; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; > +} SYNQUACER_SMMU_NODE; > + > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; > +} SYNQUACER_RC_NODE; > + > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; > + SYNQUACER_ITS_NODE ItsNode; > + //SYNQUACER_SMMU_NODE Smmu; > + SYNQUACER_RC_NODE RcNode[2]; > +} SYNQUACER_IO_REMAPPING_STRUCTURE; > + > +#define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds) \ > + { \ > + { \ > + EFI_ACPI_IORT_TYPE_SMMUv1v2, \ > + sizeof(SYNQUACER_SMMU_NODE), \ > + 0x0, \ > + 0x0, \ > + NumIds, \ > + FIELD_OFFSET(SYNQUACER_SMMU_NODE, RcIdMapping), \ > + }, \ > + Base, \ > + Size, \ > + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, \ > + 0, \ > + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ > + SMMU_NSgIrpt), \ > + 0x2, \ > + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ > + 0x0, \ > + 0x0, \ > + Irq, \ > + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ > + 0x0, \ > + 0x0, \ > + }, { \ > + { \ > + Irq, \ > + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ > + }, \ > + { \ > + Irq, \ > + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ > + }, \ > + } > + > +#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ > + { \ > + In, \ > + Num, \ > + Out, \ > + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref), \ > + Flags \ > + } > + > +STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort =3D { > + { > + __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, > + SYNQUACER_IO_REMAPPING_STRUCTURE, > + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), > + 3, // NumNodes > + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset > + 0 // Reserved > + }, { > + // ItsNode > + { > + { > + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type > + sizeof(SYNQUACER_ITS_NODE), // Length > + 0x0, // Revision > + 0x0, // Reserved > + 0x0, // NumIdMapp= ings > + 0x0, // IdReferen= ce > + }, > + 1, > + }, { > + 0x0 > + }, > + }, { > +// __SYNQUACER_SMMU_NODE(0x582C0000, 0x10000, 234, 1), > +// { __SYNQUACER_ID_MAPPING(0x200, 0x0, 0x0, ItsNode, 0x0), } > +// }, { > + // PciRcNode > + { > + { > + { > + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type > + sizeof(SYNQUACER_RC_NODE), // Length > + 0x0, // Revision > + 0x0, // Reserved > + 0x1, // NumIdMa= ppings > + FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdRefer= ence > + }, > + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCo= herent > + 0x0, // Allocat= ionHints > + 0x0, // Reserved > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryA= ccessFlags > + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttr= ibute > + 0x0, // PciSegm= entNumber > + }, { > + __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_= MAPPING_FLAGS_SINGLE), > + }, > + }, { > + // PciRcNode > + { > + { > + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type > + sizeof(SYNQUACER_RC_NODE), // Length > + 0x0, // Revision > + 0x0, // Reserved > + 0x1, // NumIdMa= ppings > + FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdRefer= ence > + }, > + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCo= herent > + 0x0, // Allocat= ionHints > + 0x0, // Reserved > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryA= ccessFlags > + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttr= ibute > + 0x1, // PciSegm= entNumber > + }, { > + __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_= MAPPING_FLAGS_SINGLE), > + } > + } > + } > +}; > + > +#pragma pack() > + > +VOID* CONST ReferenceAcpiTable =3D &Iort; > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Madt.aslc > new file mode 100644 > index 000000000000..a8c27dcf8923 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc > @@ -0,0 +1,152 @@ > +/** @file > +* Multiple APIC Description Table (MADT) > +* > +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the= BSD License > +* which accompanies this distribution. The full text of the license ma= y be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include > + > +#include "AcpiTables.h" > + > +// > +// Multiple APIC Description Table > +// > +#pragma pack (1) > + > +typedef struct { > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; > + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[Fi= xedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)]; > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; > + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor; > + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts; > +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; > + > +#pragma pack () > + > +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { > + { > + __ACPI_HEADER ( > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION > + ), > + // > + // MADT specific fields > + // > + 0, // LocalApicAddress > + 0, // Flags > + }, > + { > + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, PmuIrq, GicBase, GicVBase, > + // GicHBase, GsivId, GicRBa= se) > + // Note: The GIC Structure of the primary CPU must be the first entr= y (see note in 5.2.12.14 GICC Structure of > + // ACPI v6.0). > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 > + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1 > + 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2 > + 0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3 > + 0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4 > + 0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5 > + 0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6 > + 0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7 > + 0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8 > + 0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9 > + 0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet3= 2 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10 > + 0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11 > + 0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12 > + 0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13 > + 0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14 > + 0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15 > + 0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16 > + 0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17 > + 0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18 > + 0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19 > + 0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet= 32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20 > + 0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGe= t32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21 > + 0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGe= t32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22 > + 0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGe= t32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23 > + 0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGe= t32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */= ), > + }, > + // GIC Distributor Entry > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), 0, 3), > + // GIC Redistributor > + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), 0x300000), > + // GIC ITS > + EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000) > +}; > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving the > +// data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Madt; > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Mcfg.aslc > new file mode 100644 > index 000000000000..00df5f181de3 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc > @@ -0,0 +1,63 @@ > +/** @file > + > + ACPI Memory mapped configuration space base address Description Table = (MCFG). > + Implementation based on PCI Firmware Specification Revision 3.0 final = draft, > + downloadable at http://www.pcisig.com/home > + > + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. > + Copyright (c) 2017, Linaro Limited. All rights reserved. > + > + This program and the accompanying materials are licensed and > + made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the > + license may be found at http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > + > +**/ > + > +#include > +#include > +#include > + > +#include "AcpiTables.h" > + > +#pragma pack(push, 1) > + > +typedef struct { > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; > + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOC= ATION_STRUCTURE Structure[2]; > +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; > + > +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg= =3D { > + { > + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_= SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), > + EFI_ACPI_RESERVED_QWORD > + }, > + { > + { > + SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000, > + 0, > + SYNQUACER_PCI_SEG0_BUSNUM_MIN, > + SYNQUACER_PCI_SEG0_BUSNUM_MIN, > + EFI_ACPI_RESERVED_DWORD > + }, { > + SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000, > + 1, > + SYNQUACER_PCI_SEG1_BUSNUM_MIN, > + SYNQUACER_PCI_SEG1_BUSNUM_MIN, > + EFI_ACPI_RESERVED_DWORD > + } > + } > +}; > + > +#pragma pack(pop) > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving the > +// data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Mcfg; > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc b/Silicon/S= ocionext/SynQuacer/AcpiTables/Spcr.aslc > new file mode 100644 > index 000000000000..f51475e5c6a2 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc > @@ -0,0 +1,127 @@ > +/** @file > + > + Serial Port Console Redirection Table > + (c) 2000 - 2014 Microsoft Corporation. All rights reserved. > + http://go.microsoft.com/fwlink/?linkid=3D403368 > + > + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the = BSD License > + which accompanies this distribution. The full text of the license may= be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > + > +**/ > + > +#include > +#include > + > +#include "AcpiTables.h" > + > +#pragma pack(push, 1) > + > +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { > + // > + // Header > + // > + __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGN= ATURE, > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, > + 2), /* New MS definition for PL011 support */ > + // > + // InterfaceType > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL01= 1_UART, > + // > + // Reserved[3] > + // > + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BY= TE }, > + // > + // BaseAddress > + // > + { > + EFI_ACPI_5_1_SYSTEM_MEMORY, > + 32, > + 0, > + EFI_ACPI_5_1_DWORD, > + FixedPcdGet32 (PcdSerialRegisterBase) > + }, > + // > + // InterruptType > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, > + // > + // Irq > + // > + 0, > + // > + // GlobalSystemInterrupt > + // > + 95, > + // > + // BaudRate > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, > + // > + // Parity > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, > + // > + // StopBits > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, > + // > + // FlowControl > + // > + 0, > + // > + // TerminalType > + // > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, > + // > + // Language > + // > + EFI_ACPI_RESERVED_BYTE, > + // > + // PciDeviceId > + // > + 0xFFFF, > + // > + // PciVendorId > + // > + 0xFFFF, > + // > + // PciBusNumber > + // > + 0x00, > + // > + // PciDeviceNumber > + // > + 0x00, > + // > + // PciFunctionNumber > + // > + 0x00, > + // > + // PciFlags > + // > + 0, > + // > + // PciSegment > + // > + 0, > + // > + // Reserved2 > + // > + EFI_ACPI_RESERVED_DWORD > +}; > + > +#pragma pack(pop) > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving > +// the data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Spcr; > --=20 > 2.11.0 >=20 --u3/rZRmxL6MmkK24 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEenb+qYJ1KjE/UpmZkGKawB22KXYFAln5ntoACgkQkGKawB22 KXZlNw//WeAWsQBlG4jBmgUNswygepY4IsQTPApmESYnHKXmGPI9jx5SefFJFqtm lVGMONMYkBAbpNxwqZj6GgN5szO9hA3N16H7dgaMERxHAkyC/GQeG2U6pdatzMiE gZp8D5+BVwpzcR0WGkofMj0ynnvR6E5OUCMKIbs1HRj2HYOMvoI9fMRTsBloBABO /IaBUSn03DNiJ9R6Huev+iHVl9bVAfTPeQSIQlKnDaKMTKS6MdXrS/PSn9KV+GwY giKWwA/KbTvIAzP0INLaZvHbb2Md7W6Fw2TX1j0HqxHwagfCRYvrs1/ijXGWul8c 8tLz8ZQJvBaz7qyy7ehhdTzmpP21d8i2pZHAz93gAJAQ/6fER3usKtLwr6gseRmd SHupJjVYHTWonqGfpo3HF7iq2dUr3NkKEQl1ryWM95lDtO/AA7nCJ3zRDKRPp3ri 2OzX4o3sVoJURnpJ5MKsBX2RacjIf7oLkgKSKgtFyA0IQKODlDCh2XoniVtorTFa yg64lop+TjVog3anC0TIoTf5CGiyLL5R/U5WQbB5mMh68Wlrrl9TDOD4Jm51S1vL WuECwNwjRiGaUSH8pFoaQ0P4dPNjkgJHo6X7ol916EJzHzngHtd95snVPlenVoXN xZx1HnWxCEHmwxrrAlQ6RjupU+08buaruFGg58wBfTJnATH9HvU= =mOlS -----END PGP SIGNATURE----- --u3/rZRmxL6MmkK24--