From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CEAC12034EE00 for ; Thu, 9 Nov 2017 05:41:07 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id s66so1997401wmf.2 for ; Thu, 09 Nov 2017 05:45:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=w4rg0GtnvEjZ4+QtdIJc96DdxfsHuBebOkCG/3Y0ppU=; b=NCF4mUwEBTaNGtx7gL6iVWLVLbqyGSEfVarNAMiMhoe72BMLTrPefWpsK/RXsrfqd8 7oGCjbOteo2IaiVaS1c6z8+acK59jp63Cl4lzHmB4A+KNuUBfofI4Rr2fkPMkNhd5w3W poY1Dxy8uq0krNs0nWSXGpHP62lJWKqTjH6c0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=w4rg0GtnvEjZ4+QtdIJc96DdxfsHuBebOkCG/3Y0ppU=; b=qAUFUvdHWwU7Mqt/89blCWXdknu5L32C45HWqWRkumeHUeLwIMK3jyE2jlWbJpj/k4 JOwuVkX5861DeRH1x8C/tFl+8bjE7FrmIMjalaWGSPwntq4VT/wml7PUbeVffpl0MNFL LiA1JWWFSS8R+1OJNrVV8iAeeLDK9ujW4EILGLW/z6NSmHq21cl1y8qxIETWMaPajzbq qa9MTX0GSOdUPFR43oAGrtlAZ1gpD91TDh5jw2q9nKpkyy9m6Zq2MKroLJasfrn6xC2B s0goQH2W9g3X3JmbHmNqfQoCGZegi7Sc34CA4uoM4/RlxYWWpbT2UOAqLkSPQz07HQs5 WVdQ== X-Gm-Message-State: AJaThX5SvW6NVwBvbIkJ3FaFT2r4B2ePdxwn+zdAOn+uyyPxMchrvXLK IHcmLQipDnSCSV/8PvhJQ4qdPQ== X-Google-Smtp-Source: AGs4zMZD84mSun7AEMUI9xPvckcou5rbgNHY7+AD2vz+8jpQAtpOoNp9d7jGzwcT+fB7p3e5mwZFFQ== X-Received: by 10.28.138.12 with SMTP id m12mr453452wmd.134.1510235108203; Thu, 09 Nov 2017 05:45:08 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b23sm8522983wrg.37.2017.11.09.05.45.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Nov 2017 05:45:06 -0800 (PST) Date: Thu, 9 Nov 2017 13:44:50 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171109134450.f6lazrh7mr4bht54@bivouac.eciton.net> References: <1509879339-10516-1-git-send-email-mw@semihalf.com> <1509879339-10516-3-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1509879339-10516-3-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 2/4] Marvell/Drivers: MvSpiDxe: Enable using driver in RT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Nov 2017 13:41:08 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Nov 05, 2017 at 11:55:37AM +0100, Marcin Wojtas wrote: > This patch applies necessary modifications, which allow to use > MvSpiDxe driver in variable support as a runtime service. > Its type is modified to DXE_RUNTIME_DRIVER, as well as > a new callback is introduced as a part of the SpiMasterProtocol. > It is supposed to configure the memory space for mmio access to > the host controller registers. Moreover gBS locking usage in > MvSpiTransfer is limited to the firmware, as the runtime access > to the flash is protected within the OS. Break the commit message up a bit: --- This patch applies necessary modifications, which allow to use MvSpiDxe driver in variable support as a runtime service. Its type is modified to DXE_RUNTIME_DRIVER, as well as a new callback is introduced as a part of the SpiMasterProtocol. --- And then this needs rewording --- It is supposed to configure the memory space for mmio access to the host controller registers. --- (Say what it does, not what it should be doing.) --- Moreover gBS locking usage in MvSpiTransfer is limited to the firmware, as the runtime access to the flash is protected within the OS. --- And "is limited to the firmware". Just because it is used at runtime does not make it not firmware. I would say something like: "Apply locking in the driver only during boot services. Once at runtime, resource protection is handled by the operating system.". Also, "Its" -> "The driver's" and "It" -> "The driver". Other than that, can you move the Depex addition here from 4/4 please? / Leif > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 50 ++++++++++++++++++-- > Platform/Marvell/Drivers/Spi/MvSpiDxe.h | 2 + > Platform/Marvell/Drivers/Spi/MvSpiDxe.inf | 4 +- > Platform/Marvell/Include/Protocol/Spi.h | 7 +++ > 4 files changed, 58 insertions(+), 5 deletions(-) > > diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > index c60a520..bab6cf4 100755 > --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c > @@ -211,7 +211,9 @@ MvSpiTransfer ( > > Length = 8 * DataByteCount; > > - EfiAcquireLock (&SpiMaster->Lock); > + if (!EfiAtRuntime ()) { > + EfiAcquireLock (&SpiMaster->Lock); > + } > > if (Flag & SPI_TRANSFER_BEGIN) { > SpiActivateCs (Slave); > @@ -254,7 +256,9 @@ MvSpiTransfer ( > SpiDeactivateCs (Slave); > } > > - EfiReleaseLock (&SpiMaster->Lock); > + if (!EfiAtRuntime ()) { > + EfiReleaseLock (&SpiMaster->Lock); > + } > > return EFI_SUCCESS; > } > @@ -338,6 +342,44 @@ MvSpiFreeSlave ( > return EFI_SUCCESS; > } > > +EFI_STATUS > +EFIAPI > +MvSpiConfigRuntime ( > + IN SPI_DEVICE *Slave > + ) > +{ > + EFI_STATUS Status; > + UINTN AlignedAddress; > + > + // > + // Host register base may be not aligned to the page size, > + // which is not accepted when setting memory space attributes. > + // Add one aligned page of memory space which covers the host > + // controller registers. > + // > + AlignedAddress = Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1); > + > + Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, > + AlignedAddress, > + SIZE_4KB, > + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__)); > + return Status; > + } > + > + Status = gDS->SetMemorySpaceAttributes (AlignedAddress, > + SIZE_4KB, > + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTION__)); > + gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB); > + return Status; > + } > + > + return EFI_SUCCESS; > +} > + > STATIC > EFI_STATUS > SpiMasterInitProtocol ( > @@ -350,6 +392,7 @@ SpiMasterInitProtocol ( > SpiMasterProtocol->FreeDevice = MvSpiFreeSlave; > SpiMasterProtocol->Transfer = MvSpiTransfer; > SpiMasterProtocol->ReadWrite = MvSpiReadWrite; > + SpiMasterProtocol->ConfigRuntime = MvSpiConfigRuntime; > > return EFI_SUCCESS; > } > @@ -363,8 +406,7 @@ SpiMasterEntryPoint ( > { > EFI_STATUS Status; > > - mSpiMasterInstance = AllocateZeroPool (sizeof (SPI_MASTER)); > - > + mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (SPI_MASTER)); > if (mSpiMasterInstance == NULL) { > return EFI_OUT_OF_RESOURCES; > } > diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h > index e7e280a..50cdc02 100644 > --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h > +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h > @@ -38,10 +38,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #include > #include > #include > +#include > #include > #include > #include > #include > +#include > > #include > > diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf b/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf > index 08c6c04..9fe246f 100644 > --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf > +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf > @@ -33,7 +33,7 @@ > INF_VERSION = 0x00010005 > BASE_NAME = SpiMasterDxe > FILE_GUID = c19dbc8a-f4f9-43b0-aee5-802e3ed03d15 > - MODULE_TYPE = DXE_DRIVER > + MODULE_TYPE = DXE_RUNTIME_DRIVER > VERSION_STRING = 1.0 > ENTRY_POINT = SpiMasterEntryPoint > > @@ -53,8 +53,10 @@ > TimerLib > UefiLib > DebugLib > + DxeServicesTableLib > MemoryAllocationLib > IoLib > + UefiRuntimeLib > > [FixedPcd] > gMarvellTokenSpaceGuid.PcdSpiRegBase > diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Include/Protocol/Spi.h > index d993021..abbad19 100644 > --- a/Platform/Marvell/Include/Protocol/Spi.h > +++ b/Platform/Marvell/Include/Protocol/Spi.h > @@ -101,12 +101,19 @@ EFI_STATUS > IN SPI_DEVICE *SpiDev > ); > > +typedef > +EFI_STATUS > +(EFIAPI *MV_SPI_CONFIG_RT) ( > + IN SPI_DEVICE *SpiDev > + ); > + > struct _MARVELL_SPI_MASTER_PROTOCOL { > MV_SPI_INIT Init; > MV_SPI_READ_WRITE ReadWrite; > MV_SPI_TRANSFER Transfer; > MV_SPI_SETUP_DEVICE SetupDevice; > MV_SPI_FREE_DEVICE FreeDevice; > + MV_SPI_CONFIG_RT ConfigRuntime; > }; > > #endif // __MARVELL_SPI_MASTER_PROTOCOL_H__ > -- > 2.7.4 >