From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9CDD82035521F for ; Fri, 10 Nov 2017 06:18:40 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id y9so8758086wrb.2 for ; Fri, 10 Nov 2017 06:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=its2kpmC9jMrjP++ef6qSkrsn5mU0zjDLrsOXXhd76s=; b=XL4pv01QhoAWCXvESwNLC2KnGUaPrYWqeCFZ0QBhA6DppcMDzw7Z8HzcKOGuH4YbX4 1F6eyJpqcfpEEmsqv2Dszw5Xkb0lqxsFZb/tO5vGgwkn2ss62g5h5Iw2BFQv9KwHME+C pjYT7gesSFDsjMfdsMvNiei6C9ju53Sgu4/Yk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=its2kpmC9jMrjP++ef6qSkrsn5mU0zjDLrsOXXhd76s=; b=nGK/xNsqH3yxnSSuj9Znd50WuN45C7dKYbwuhvo2ziFwsjb0HBQuKFsBg8YGHhUYkA JEKBpuG9DsQqYvJAQGKEOjgnhZ6J3KsFwtUhwFBGlHoaVLwZzt2md/8qEQMzK4UPIOOH SWb1TFRSX/0d+wojeO9bLuMzWao0k5D6jEYqk1gkMuJVBpRL3AGWXIZUifpwygN+ffVv Kutj1l32jlC7h/+QXiwAEjWsg/ZDwpo31eQrqRgHpiwYmtjNJyxcKq7Ezfzm1v6Wif8z krlwuhpIGDLZI26uZcTAxGXReEJSVdS7n4w4X4QN6K9Rov+OupnpTMCRySS4EkRmUzYV Xm3Q== X-Gm-Message-State: AJaThX76N9SmayiQ96I2PiNqcj0drxvLlZkHqk2FNVXQX8Nm+cY2vY0C z4exuMtffM426r/AGqh/0XyTpz3N/8s= X-Google-Smtp-Source: AGs4zMYFJpKMtBejvczJcFdZfheNOChr0vGvIWeDeTuWdhI6R0Ef6VDi6olv2ZtouQ0MFqc744kKyg== X-Received: by 10.223.160.230 with SMTP id n35mr517395wrn.116.1510323762112; Fri, 10 Nov 2017 06:22:42 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.22.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:41 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Cc: masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Fri, 10 Nov 2017 14:21:14 +0000 Message-Id: <20171110142127.12018-22-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v4 21/34] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Nov 2017 14:18:41 -0000 Implement workaround suggested by Socionext to get legacy endpoints with 32-bit BARs working. This fixes the issue on Developer Box with the onboard ASM1061 SATA controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index b5bfea8e0e75..1bbef5b6cf98 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -32,10 +32,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 @@ -297,8 +300,9 @@ PciInitController ( RootBridge->Mem.Base, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); // Region 1: Type 0 config space ConfigureWindow (DbiBase, 1, -- 2.11.0