From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 37E622035521F for ; Fri, 10 Nov 2017 06:18:53 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id r68so6058157wmr.0 for ; Fri, 10 Nov 2017 06:22:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2j6jrZsJ+Me82rmvZCrCaGtWmj08YhcSV+W4KHRzXUs=; b=ji0p192sp+o+ybBrXFzV8mdZmEGCZA20tuHuuwT6EA8V3hc6jY8HrLrwt84SDZgRba vndip7Dece9x3DxA8jeUU7TUmS9mGScgjphXV3/eIISKhgUV7xzgPfZ8RA2mxU3hr4D9 xVTr5rcbAzFJvZYL+lWR2GS9HFHD32dH0CBiY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2j6jrZsJ+Me82rmvZCrCaGtWmj08YhcSV+W4KHRzXUs=; b=YOFZ3Eilap2afoIXkjxeH/ieBqmN5udyIhcohq5p7bHV1NxyNL1tQD2eOAZY0Y3VQr SjrHs++FULhjdBTI9eSw0pJD8iJlc4WfpkneB9EsvdmjJbgE0d1zoRpAlwEAkNatThcD frNnl10GtQ/IuN3UrRb7LpHO9mDsPWj7o9KDYrXBAXF/iRqXt+ovsaV5wQWBoygasPaL hqchv0J5ydP4ZbrLbg8rBYvITJ/sTkRnxtTtJEP9CN5SVRrkRd3v+VhhKjiJfzoRW8en 9DAEUFoY5zfkpwE7maGGKS5C3pNUZ75uAU8D39hXpioIq3trLjiUOPcyPW4bSYZvbT/s MUYA== X-Gm-Message-State: AJaThX6S1Ho5Z4lbnby6IRyjkwjorIPmMUJPkRG7Zg0IqsUPt/Jpk3hr fvvgXYQGJ+DVoOt4Vq+UxEUfnC53Ne8= X-Google-Smtp-Source: AGs4zMbo2ld1SeEFvjMryJjzHV/xZKKqkAlmQCveZIjhr2J984Ke3QJSWLSU02nlLTTkpP90wwZKjg== X-Received: by 10.28.60.68 with SMTP id j65mr368848wma.16.1510323774674; Fri, 10 Nov 2017 06:22:54 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.22.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:53 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Cc: masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Fri, 10 Nov 2017 14:21:19 +0000 Message-Id: <20171110142127.12018-27-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v4 26/34] Silicon/SynQuacer: add DT description of the SDHCI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Nov 2017 14:18:53 -0000 Describe the SynQuacer SoC's eMMC controller in DT so the OS can attach to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index e72db377bc39..cf06acc75297 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -532,4 +532,30 @@ #interrupt-cells = <3>; socionext,spi-base = <112>; }; + + clk_alw_b_0: bclk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "sd_bclk"; + }; + + clk_alw_c_0: sd4clk800 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sd_sd4clk"; + }; + + sdhci@52300000 { + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; + reg = <0 0x52300000 0x0 0x1000>; + interrupts = , + ; + bus-width = <8>; + cap-mmc-highspeed; + fujitsu,cmd-dat-delay-select; + clocks = <&clk_alw_c_0 &clk_alw_b_0>; + clock-names = "core", "iface"; + }; }; -- 2.11.0