From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9987E2035BB03 for ; Thu, 16 Nov 2017 09:54:57 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id l22so23586264wrc.11 for ; Thu, 16 Nov 2017 09:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ij98T+295s/mMLYfruGkuKyl8WfhM9bBGM1FCqF0ZA=; b=UAbNFD76dG7T76CXf4Kw/tMcTzNPf/E5yZCHKwfVuT4m2b6v5QSUKRMOqKaXTN5aMG r0imkVHLxqj60UY5yNCM+yLKj9MWgM14OIKXLnN/uO23s99tjkm2uDVHv8yYuEr10XFk q6/LC+SNpckcZuaFUs5zlCcHJesKdwRevN8FY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ij98T+295s/mMLYfruGkuKyl8WfhM9bBGM1FCqF0ZA=; b=uD/EqpTRgrP8tgkmV4QYLdxh3QzUGhIxnwE0Dz06RFMXT9ShYHhzBjOs3A8f1QEgLD U4QFmA860vEA/NA9k7Bg+7fy/WWX6xay8eq4p7ttb1MmJYiirgpHeoi/ppudf1YnZBsB kym1+mgqVPY2nym5E+ETzk9SJPi1bwUKat8b5ZUQs0P90vjtKiHSa7PqDjxqrSxT/ghG 1ImORW5NF2X/dxE5z6832RwxtQ/5KJdmZfLNq/bXqEqPljX/tEMP+mcx4C4V0aSpA5b4 +6gpecMz8FaO3LFhVnxxT68sauqd1QK16H5dd7T35TPc/9woASKa5qRD9Mj43+RCmpOB NFrw== X-Gm-Message-State: AJaThX6wbRQm82BFaEW3iZ6U8rbdQkRKAMPok0lEpbqn3XkpMV/BaDyG AvnSSnMZ5/EnW4RMcXdCm72xXszPLVE= X-Google-Smtp-Source: AGs4zMaHWKaSXcKfcc7GHKnY7RQ2Oizn3V5ovGhPjO+HFLM4pMqnLYO2K7cCjiQ9aTEj5/kt+hAfbA== X-Received: by 10.223.186.66 with SMTP id t2mr2166621wrg.275.1510855145823; Thu, 16 Nov 2017 09:59:05 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id k13sm1638610wrd.95.2017.11.16.09.59.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Nov 2017 09:59:04 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: Ard Biesheuvel Date: Thu, 16 Nov 2017 17:58:38 +0000 Message-Id: <20171116175839.30012-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171116175839.30012-1-ard.biesheuvel@linaro.org> References: <20171116175839.30012-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v2 08/13] Platform/Hisilicon: remove SP804 PCD definitions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2017 17:54:58 -0000 These platforms don't actually include the SP804 driver so no need to set the PCDs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Hisilicon/D02/Pv660D02.dsc | 8 -------- Platform/Hisilicon/D03/D03.dsc | 8 -------- 2 files changed, 16 deletions(-) diff --git a/Platform/Hisilicon/D02/Pv660D02.dsc b/Platform/Hisilicon/D02/Pv660D02.dsc index ba3047882611..cd0fbdb56fdf 100644 --- a/Platform/Hisilicon/D02/Pv660D02.dsc +++ b/Platform/Hisilicon/D02/Pv660D02.dsc @@ -201,14 +201,6 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } - ## SP804 DualTimer - gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|304 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x80060000 - ## TODO: need to confirm the base for Performance and Metronome base for PV660 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x80060000 - gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x80060000 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x6 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3 gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000 # 4T diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 491862a3b27e..a5aa5f7fcd0a 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -286,14 +286,6 @@ [PcdsFixedAtBuild.common] gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K gHisiTokenSpaceGuid.Pcdsoctype|0x1610 - ## SP804 DualTimer - gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0xb0 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x40060000 - ## TODO: need to confirm the base for Performance and Metronome base for PV660 - gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 - gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000 - ################################################################################ # -- 2.11.0