From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 601CC20349DAC for ; Fri, 17 Nov 2017 07:12:14 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id u40so2374749wrf.10 for ; Fri, 17 Nov 2017 07:16:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=buFUCAwbK9kiiRJ6aNJN68lh8dnrjaUCt7AuVz5mzXM=; b=MxMIHxnAA022tdgbw6RE4KYqxFm2qSqt11swrbhNKBO/U0EddD4sEkzp87cBPbAKop fsXm3uUPgOzxKGgun8gFypgVhxwA8Dm+c0V5P/iKBa0/gGDvjhf4TutZ8LZxZtf07QMP P1QVS5p6/UwZN30nfPVkLmV49Q/HlSyC9kZi4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=buFUCAwbK9kiiRJ6aNJN68lh8dnrjaUCt7AuVz5mzXM=; b=IzFC75x8c+KxjqHiZgktNEWOToZIoohBiiWYl6mqkHGDlnmwTvIJzDff1A+aVyeLvY 2r1UxoHbJQt00broZnawGRSNWe9snGZTs4RvZ3g1EMxAnxW0+bKE/NALFmiHYrl6c+Ny NwUIzvsjKXH2E/EavVp4w0bpWXE5WWoktNAJWXyeilabTnkbZqw2WH3QZmmU34/Gyrfr eBwKKxiDJRe41ohNQqG9SLnvCaBZdKYaryA9mp5ZUYGbqAYNbHUq24ZMqXTyfklVDIDv kZlyp4L3ewV3VwpxAGoM0M0KobSZoxVxjqhwvH/KR/3+4nm4MucSg+zTN8Wcx+rZ3wrh 1odg== X-Gm-Message-State: AJaThX6lJsowZJqmr+2lXoRh6ftC1XtWq4IDuAS2hYF4IXpJt/KO2LuL swmMzgAnh2c/BLWmSOwyqYMSlA== X-Google-Smtp-Source: AGs4zMZ25S6XlxLJYMa/AI8F4NvtBxClj8hocFl69ETz1/vJyHaa9X2NooaBOPT6JrbmqbZPnAWlKg== X-Received: by 10.223.183.17 with SMTP id l17mr4964439wre.1.1510931783776; Fri, 17 Nov 2017 07:16:23 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id r14sm7879635wrb.43.2017.11.17.07.16.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 17 Nov 2017 07:16:22 -0800 (PST) Date: Fri, 17 Nov 2017 15:16:20 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org Message-ID: <20171117151620.vsfkzsy73cz5z2rf@bivouac.eciton.net> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> <20171110142127.12018-27-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171110142127.12018-27-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v4 26/34] Silicon/SynQuacer: add DT description of the SDHCI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Nov 2017 15:12:14 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Nov 10, 2017 at 02:21:19PM +0000, Ard Biesheuvel wrote: > Describe the SynQuacer SoC's eMMC controller in DT so the OS can > attach to it. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel So, slightly obnoxious, but... Since this is the .dtsi for the SoC as a whole, is there any convenient way for us to selectively exclude this bit when building? Some platforms may not use this, and some may chose not to expose it to the OS. / Leif > --- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 26 ++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index e72db377bc39..cf06acc75297 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -532,4 +532,30 @@ > #interrupt-cells = <3>; > socionext,spi-base = <112>; > }; > + > + clk_alw_b_0: bclk200 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + clock-output-names = "sd_bclk"; > + }; > + > + clk_alw_c_0: sd4clk800 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <800000000>; > + clock-output-names = "sd_sd4clk"; > + }; > + > + sdhci@52300000 { > + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; > + reg = <0 0x52300000 0x0 0x1000>; > + interrupts = , > + ; > + bus-width = <8>; > + cap-mmc-highspeed; > + fujitsu,cmd-dat-delay-select; > + clocks = <&clk_alw_c_0 &clk_alw_b_0>; > + clock-names = "core", "iface"; > + }; > }; > -- > 2.11.0 >