Re: [PATCH edk2-platforms v4 29/34] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch

[Leif Lindholm <leif.lindholm@linaro.org>]

On Fri, Nov 17, 2017 at 05:42:30PM +0000, Ard Biesheuvel wrote:
> On 17 November 2017 at 16:10, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > And use a local variable Pin, initialized to
> > FixedPcdGet32 (PcdClearSettingsGpioPin) - 1?
> > (You could then also have an assert verifying PcdClearSettingsGpioPin
> > != 0, to make fallback to default value flash warnings.)
> 
> Right. The DEBUG build already produces the NorFlashDxe blurb that the
> FV is being reinitialized.
> 
> In any case, given that the SoC does number its GPIOs 0 - 31, the fact
> that developerbox DSW3 pins are 1 based does not mean 0 is
> unallocated.

Ah, OK, I was missing that bit.

> So I think it would make more sense to use UINT32_MAX as unused.

UINT32_MAX is a lot less ambiguous, yes.

> > And add a small comment for this line that this refers to block 3 and
> > 0 means "don't use"?
> 
> Block 3 is platform specific not SoC specific.

Another bit I was missing.
Right, and you make this even more clear in the follow-up reply.

/
    Leif