From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::231; helo=mail-wm0-x231.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8B5B3220C1C21 for ; Thu, 23 Nov 2017 04:47:01 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id 128so16315646wmo.3 for ; Thu, 23 Nov 2017 04:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=g9B8f0ge+w8q50+tJqTNQLb+bHnV0bQIg8nrcjCGzm8=; b=Kc/IJCtR5WM6AO5zH/zB2NyQ7xpYuAMfdM+M2qGoHC+4GV4ZTmpvEcppRealCfWyhW fB09XMbR2JBNajbRKam1JfvwW62HP4CA7NuRWTXF807T6CArYv6S4pvU80Iy/pNaI81b jY4bYSL405sJgmROAzJ/T819QKFwr5k5KlQVQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=g9B8f0ge+w8q50+tJqTNQLb+bHnV0bQIg8nrcjCGzm8=; b=KQ7EMGJR6HJ/6lMPQcBAR6G1XrkovWTVJrdVWaJG72SjGHRHP9L0ZL2vjtwk3Z1zhZ UXXeHoHGUQc9oxyTXI7BUSzoqLdvnGbWT8uZy8wjWcgtFiSSUx10olpSQj1hurFZUGB6 0xYT9Ua5G0P5Jm3ZotcNR8chJE3h544Wm4WQ797K7y5q26g3T1kgzZWbYDnNtffy6Z9H z+h4QkolDeXnqPfGXkifx+oDjY4knV4GEHSz2To/JfpmfpwCbEyS7rdZuQiPOAT+5+jW YbR3Du/zdBG+RAMBOeCuZQkirSKVoFM+hb032tcnMX5nXA4dcvrIv6VI1XnAr7SFYKGd 9RqA== X-Gm-Message-State: AJaThX56/i01a0Lef4eD8BVU3utsp+xMvvP6kKylMLTxXKoAnCTOhrgp MW5Idtp7EDI35/OyuGyuxjItvg== X-Google-Smtp-Source: AGs4zMapFKt6zGlZSIN+m2qEXmgVyTDlHjSiq5JAmX4cT77FxZPr3EsWdSKqXqvcMyuc9fSuu9GQSQ== X-Received: by 10.28.7.133 with SMTP id 127mr6766010wmh.31.1511441477505; Thu, 23 Nov 2017 04:51:17 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j10sm7251474wrh.32.2017.11.23.04.51.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2017 04:51:16 -0800 (PST) Date: Thu, 23 Nov 2017 12:51:14 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu , =?utf-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= , Masahisa Kojima Message-ID: <20171123125114.j5h3wmryafeyogiy@bivouac.eciton.net> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> <20171110142127.12018-30-ard.biesheuvel@linaro.org> <20171117161046.uaxf4qhjzkdupzd5@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v4 29/34] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Nov 2017 12:47:01 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Nov 17, 2017 at 05:42:30PM +0000, Ard Biesheuvel wrote: > On 17 November 2017 at 16:10, Leif Lindholm wrote: > > And use a local variable Pin, initialized to > > FixedPcdGet32 (PcdClearSettingsGpioPin) - 1? > > (You could then also have an assert verifying PcdClearSettingsGpioPin > > != 0, to make fallback to default value flash warnings.) > > Right. The DEBUG build already produces the NorFlashDxe blurb that the > FV is being reinitialized. > > In any case, given that the SoC does number its GPIOs 0 - 31, the fact > that developerbox DSW3 pins are 1 based does not mean 0 is > unallocated. Ah, OK, I was missing that bit. > So I think it would make more sense to use UINT32_MAX as unused. UINT32_MAX is a lot less ambiguous, yes. > > And add a small comment for this line that this refers to block 3 and > > 0 means "don't use"? > > Block 3 is platform specific not SoC specific. Another bit I was missing. Right, and you make this even more clear in the follow-up reply. / Leif