From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90E642034C5F4 for ; Thu, 23 Nov 2017 19:29:25 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Nov 2017 19:33:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,444,1505804400"; d="scan'208";a="5195214" Received: from zwei4-mobl1.ccr.corp.intel.com ([10.239.193.136]) by FMSMGA003.fm.intel.com with ESMTP; 23 Nov 2017 19:33:42 -0800 From: zwei4 To: edk2-devel@lists.01.org Date: Fri, 24 Nov 2017 11:33:26 +0800 Message-Id: <20171124033327.7244-3-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171124033327.7244-1-david.wei@intel.com> References: <20171124033327.7244-1-david.wei@intel.com> Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017 3/4] Board Specific Code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Nov 2017 03:29:25 -0000 Add BoardInitPreMem lib for Minnowboard3 Next pre-production board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 --- .../MinnowBoard3Next/BoardInitPreMem/BoardInit.c | 190 +++++++++ .../MinnowBoard3Next/BoardInitPreMem/BoardInit.h | 29 ++ .../BoardInitPreMem/BoardInitMiscs.c | 433 +++++++++++++++++++++ .../BoardInitPreMem/BoardInitMiscs.h | 67 ++++ .../BoardInitPreMem/BoardInitPreMem.inf | 62 +++ .../MinnowBoard3Next/BoardInitPreMem/PlatformId.c | 231 +++++++++++ .../MinnowBoard3Next/BoardInitPreMem/PlatformId.h | 45 +++ 7 files changed, 1057 insertions(+) create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.h create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.c create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.h create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.c create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.h diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c new file mode 100644 index 000000000..7df8fd1c0 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.c @@ -0,0 +1,190 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "BoardInit.h" +#include "PlatformId.h" +#include "BoardInitMiscs.h" + +EFI_STATUS +EFIAPI +MinnowBoard3NextPreMemInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_BOARD_PRE_MEM_INIT_PPI *This + ); + +static PEI_BOARD_PRE_MEM_INIT_PPI mMinnow3NextPreMemInitPpiInstance = { + MinnowBoard3NextPreMemInit +}; + +static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitPpi = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardPreMemInitPpiGuid, + &mMinnow3NextPreMemInitPpiInstance +}; + +static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitDonePpi = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardPreMemInitDoneGuid, + NULL +}; + +EFI_STATUS +EFIAPI +MinnowBoard3NextPreMemInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_BOARD_PRE_MEM_INIT_PPI *This + ) +{ + EFI_STATUS Status; + VOID *Instance; + UINT8 BoardId; + UINT8 FabId; + + BoardId = 0; + FabId = 0; + Status = PeiServicesLocatePpi ( + &gBoardPreMemInitDoneGuid, + 0, + NULL, + &Instance + ); + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Minnow Board 3 Next Pre Mem Init: Skip\n")); + return EFI_SUCCESS; + } + + DEBUG ((EFI_D_INFO, "Minnow Board 3 Next Pre Mem Init\n")); + + // + // Pre Mem Board Init + // + Status = Minnow3NextGetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId); + + if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) { + + return EFI_SUCCESS; + } + DEBUG ((EFI_D_INFO, "This is MinnowBoard3 Next\n")); + + PcdSet8 (PcdBoardId, BoardId); + PcdSet8 (PcdFabId, FabId); + + // + //PcdSet8 (PcdSerialIoUartNumber, 0); + // + + // + // Set board specific function as dynamic PCD to be called by common platform code + // + PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mMb3NUpdateFspmUpdPtr); + PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mMb3NDramCreatePolicyDefaultsPtr); + PcdSet64 (PcdUpdatePcieConfigFunc, (UINT64) (UINTN) mMb3NUpdatePcieConfigPtr); + + // + // Install a flag signalling a board is detected and pre-mem init is done + // + Status = PeiServicesInstallPpi (&mMinnowBoard3NextPreMemInitDonePpi); + + return EFI_SUCCESS; +} + + +/** + This function performs Board initialization in Pre-Memory. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory). + +**/ +EFI_STATUS +EFIAPI +MinnowBoard3NextInitConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + VOID *Ppi; + EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; + UINTN Instance; + + DEBUG ((EFI_D_INFO, "MinnowBoard3Next Pre Mem Init Constructor \n")); + + Status = PeiServicesLocatePpi ( + &gBoardPreMemInitDoneGuid, + 0, + &PeiPpiDescriptor, + &Ppi + ); + if (!EFI_ERROR (Status)) { + // + // Board detection previously done, so this is a re-invocation shadowed in memory. + // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM. + // + // + // Reinstall PreMemInit Done PPI + // + DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n")); + Status = PeiServicesReInstallPpi ( + PeiPpiDescriptor, + &mMinnowBoard3NextPreMemInitDonePpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Reinstall all instances of Pre Mem Init PPIs. + // These PPIs are no longer used so it doesn't matter which board's instance is finally installed. + // According to PeiServicesReInstallPpi behavior: + // The first run of this loop would replace all descrioptors with a singe in-RAM descriptor; + // Subsequent runs of this loop will only replace the first (already in-RAM) descriptor. + // As long as all descriptors are in ram, we are fine. + // + Instance = 0; + do { + Status = PeiServicesLocatePpi ( + &gBoardPreMemInitPpiGuid, + Instance, + &PeiPpiDescriptor, + &Ppi + ); + if (Status == EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR (Status); + DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n")); + Status = PeiServicesReInstallPpi ( + PeiPpiDescriptor, + &mMinnowBoard3NextPreMemInitPpi + ); + ASSERT_EFI_ERROR (Status); + + Instance++; + } while (TRUE); + return Status; + } + + DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n")); + Status = PeiServicesInstallPpi (&mMinnowBoard3NextPreMemInitPpi); + return Status; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.h new file mode 100644 index 000000000..510d053d2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInit.h @@ -0,0 +1,29 @@ +/** @file + GPIO setting for CherryView. + This file includes package header files, library classes. + + Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MINNOW_NEXT_BOARDINIT_H_ +#define _MINNOW_NEXT_BOARDINIT_H_ + +#include +#include +#include +#include +#include + +VOID MinnowNextGpioTest (VOID); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.c new file mode 100644 index 000000000..888b31668 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.c @@ -0,0 +1,433 @@ +/** @file + This file does Multiplatform initialization. + + Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BoardInitMiscs.h" + +UPDATE_FSPM_UPD_FUNC mMb3NUpdateFspmUpdPtr = Mb3NUpdateFspmUpd; +DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3NDramCreatePolicyDefaultsPtr = Mb3NDramCreatePolicyDefaults; +UPDATE_PCIE_CONFIG_FUNC mMb3NUpdatePcieConfigPtr = Mb3NUpdatePcieConfig; + +// +// Minnow Board Next swizzling +// +UINT8 ChSwizzle_MB3N[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = { + {0x00,0x06,0x04,0x05,0x01,0x03,0x02,0x07,0x08,0x09,0x0B,0x0F,0x0A,0x0D,0x0C,0x0E,0x1C,0x18,0x1A,0x1B,0x1D,0x1E,0x1F,0x19,0x12,0x13,0x14,0x11,0x10,0x16,0x17,0x15}, // Channel 0 + {0x0E,0x0F,0x0A,0x0B,0x08,0x0D,0x0C,0x09,0x07,0x04,0x05,0x00,0x01,0x03,0x02,0x06,0x12,0x15,0x14,0x17,0x10,0x13,0x11,0x16,0x1D,0x1C,0x1F,0x1B,0x1A,0x19,0x18,0x1E}, // Channel 1 + {0x0B,0x0D,0x0C,0x0F,0x09,0x08,0x0A,0x0E,0x05,0x06,0x03,0x07,0x00,0x01,0x02,0x04,0x17,0x11,0x10,0x13,0x14,0x16,0x15,0x12,0x19,0x1B,0x1A,0x18,0x1C,0x1D,0x1E,0x1F}, // Channel 2 + {0x07,0x01,0x02,0x03,0x04,0x05,0x06,0x00,0x0E,0x0D,0x0B,0x0C,0x0A,0x08,0x0F,0x09,0x1E,0x18,0x1C,0x1D,0x1A,0x19,0x1B,0x1F,0x14,0x11,0x12,0x16,0x13,0x15,0x17,0x10} // Channel 3 +}; + +BOARD_CHANNEL_INFO gMb3nChannelInfo[] = { + // DeviceWidth DramDensity Option RankEnable DescString + // Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 + {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x00, 0x00}, "LPDDR4 8Gbit 2 channels"}, // #1 - LPDDR4 8Gbit 2 channels + {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x01, 0x01}, "LPDDR4 8Gbit 4 channels"}, // #2 - LPDDR4 8Gbit 4 channels + {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x00, 0x00}, "LPDDR4 16Gbit 2 channels"}, // #3 - LPDDR4 16Gbit 2 channels + {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x03, 0x03}, "LPDDR4 16Gbit 4 channels"}, // #4 - LPDDR4 16Gbit 4 channels +}; + +EFI_STATUS +EFIAPI +Mb3NUpdateFspmUpd ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN FSPM_UPD *FspUpdRgn + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL; + DRAM_POLICY_PPI *DramPolicy; + EFI_STATUS Status; + MRC_PARAMS_SAVE_RESTORE *MrcNvData; + BOOT_VARIABLE_NV_DATA *BootVariableNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; + SYSTEM_CONFIGURATION SystemConfiguration; + UINTN VariableSize; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + UINT32 VidDid; + UINT32 HwconfStraps; + UINT8 MemoryType; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gDramPolicyPpiGuid, + 0, + NULL, + (VOID **) &DramPolicy + ); + + if (!EFI_ERROR (Status)) { + FspUpdRgn->FspmConfig.Package = DramPolicy->Package; + FspUpdRgn->FspmConfig.Profile = DramPolicy->Profile; + FspUpdRgn->FspmConfig.MemoryDown = DramPolicy->MemoryDown; + FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize; + FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR; + FspUpdRgn->FspmConfig.MemorySizeLimit = DramPolicy->SystemMemorySizeLimit; + FspUpdRgn->FspmConfig.DIMM0SPDAddress = DramPolicy->SpdAddress[0]; + FspUpdRgn->FspmConfig.DIMM1SPDAddress = DramPolicy->SpdAddress[1]; + FspUpdRgn->FspmConfig.DDR3LPageSize = DramPolicy->DDR3LPageSize; + FspUpdRgn->FspmConfig.DDR3LASR = DramPolicy->DDR3LASR; + FspUpdRgn->FspmConfig.HighMemoryMaxValue = DramPolicy->HighMemMaxVal; + FspUpdRgn->FspmConfig.LowMemoryMaxValue = DramPolicy->LowMemMaxVal; + FspUpdRgn->FspmConfig.DisableFastBoot = DramPolicy->DisableFastBoot; + FspUpdRgn->FspmConfig.RmtMode = DramPolicy->RmtMode; + FspUpdRgn->FspmConfig.RmtCheckRun = DramPolicy->RmtCheckRun; + FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold = DramPolicy->RmtMarginCheckScaleHighThreshold; + FspUpdRgn->FspmConfig.MsgLevelMask = DramPolicy->MsgLevelMask; + + FspUpdRgn->FspmConfig.ChannelHashMask = DramPolicy->ChannelHashMask; + FspUpdRgn->FspmConfig.SliceHashMask = DramPolicy->SliceHashMask; + FspUpdRgn->FspmConfig.ChannelsSlicesEnable = DramPolicy->ChannelsSlicesEnabled; + FspUpdRgn->FspmConfig.ScramblerSupport = DramPolicy->ScramblerSupport; + FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode; + FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled; + FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled; + + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) { + DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n")); + MrcNvData = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE)); + BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA)); + + MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr); + BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr); + + CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE)); + CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData; + FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData; + } + } else { + DEBUG ((DEBUG_INFO, "UpdateFspmUpd - LocatePpi(gDramPolicyPpiGuid) returned %r\n", Status)); + } + + DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n")); + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw != NULL); + PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw); + + // + // Get IGD VID/DID + // + VidDid = MmioRead32 (MmPciBase (SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0) + R_SA_IGD_VID); + if (VidDid == 0x5A848086) { + // + // E3950 path + // + DEBUG ((DEBUG_INFO, "**** MB3N - E3950 detected!\n")); + } else if (VidDid == 0x5A858086) { + // + // E3930 path + // + DEBUG ((DEBUG_INFO, "**** MB3N - E3930 detected!\n")); + } + + // + // Overrides for MinnowBoard3Next from Platfrom4 profile + // + // Description | DualRank | RankEnable | DeviceWidth | DramDenisty | SoC | Channel + // ================|==========|============|=============|=============|=======|========= + // MT53B256M32D1 | 0x01 | 0x01 | 0x01 x16 | 0x02 8Gb | E3930 | Ch0 + // MT53B512M32D2 | 0x01 | 0x03 | 0x01 x16 | 0x02 8Gb | E3950 | Ch0&1 + // MT53B1024M32D4 | 0x01 | 0x03 | 0x00 x8 | 0x04 16Gb | | + // + + // + // Get HWCONF straps + // + HwconfStraps = Minnow3NextGetHwconfStraps (); + DEBUG ((DEBUG_INFO, "**** MB3N - HWCONF straps = 0x%08X\n", HwconfStraps)); + + // + // Translate into Memory Type + // + MemoryType = (UINT8) ((HwconfStraps >> 6) & 0x07); + if (MemoryType == 0) { + DEBUG ((DEBUG_INFO, "**** MB3N - SPD based memory init requested, but converted into Memory Profile type #4!\n")); + MemoryType = 4; + } + MemoryType--; // Zero base it for use as index into array + + // + // Common items + // + FspUpdRgn->FspmConfig.Package = 0x01; + FspUpdRgn->FspmConfig.Profile = 0x09; // 0x0B; // LPDDR4_2400_24_22_22 + FspUpdRgn->FspmConfig.MemoryDown = 0x01; + FspUpdRgn->FspmConfig.DualRankSupportEnable = 0x01; + + // + // Memory Type specific items + // + if (MemoryType < (sizeof (gMb3nChannelInfo) / sizeof (gMb3nChannelInfo[0]))) { + DEBUG ((DEBUG_INFO, "**** MB3N - %a detected!\n", gMb3nChannelInfo[MemoryType].DescString)); + + // DDR0CH0 + FspUpdRgn->FspmConfig.Ch0_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[0]; + FspUpdRgn->FspmConfig.Ch0_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[0]; + FspUpdRgn->FspmConfig.Ch0_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[0]; + FspUpdRgn->FspmConfig.Ch0_Option = gMb3nChannelInfo[MemoryType].Option[0]; + + // DDR0CH1 + FspUpdRgn->FspmConfig.Ch1_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[1]; + FspUpdRgn->FspmConfig.Ch1_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[1]; + FspUpdRgn->FspmConfig.Ch1_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[1]; + FspUpdRgn->FspmConfig.Ch1_Option = gMb3nChannelInfo[MemoryType].Option[1]; + + // DDR1CH0 + FspUpdRgn->FspmConfig.Ch2_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[2]; + FspUpdRgn->FspmConfig.Ch2_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[2]; + FspUpdRgn->FspmConfig.Ch2_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[2]; + FspUpdRgn->FspmConfig.Ch2_Option = gMb3nChannelInfo[MemoryType].Option[2]; + + // DDR1CH1 + FspUpdRgn->FspmConfig.Ch3_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[3]; + FspUpdRgn->FspmConfig.Ch3_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[3]; + FspUpdRgn->FspmConfig.Ch3_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[3]; + FspUpdRgn->FspmConfig.Ch3_Option = gMb3nChannelInfo[MemoryType].Option[3]; + } else { + DEBUG ((DEBUG_INFO, "**** MB3N - Memory Type 0x%02X is out of range!\n", MemoryType)); + } + + // + // Swizzling + // + if (ChSwizzle_MB3N != NULL) { + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_MB3N[0], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_MB3N[1], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_MB3N[2], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_MB3N[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + } + + // + // Disable NPK based on DciEn + // + Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi); + if (!EFI_ERROR (Status)) { + VariableSize = sizeof (SYSTEM_CONFIGURATION); + Status = VariablePpi->GetVariable ( + VariablePpi, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + if (!EFI_ERROR (Status)) { + if (SystemConfiguration.DciEn == 0) { + FspUpdRgn->FspmConfig.NpkEn = 0; + } else if (SystemConfiguration.DciAutoDetect == 1) { + FspUpdRgn->FspmConfig.NpkEn = 3; + } else { + FspUpdRgn->FspmConfig.NpkEn = 1; + } + } + } + + return EFI_SUCCESS; +} + + +/** + DramCreatePolicyDefaults creates the default setting of Dram Policy. + + @param[out] DramPolicyPpi The pointer to get Dram Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +Mb3NDramCreatePolicyDefaults ( + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi, + OUT DRAM_POLICY_PPI **DramPolicyPpi, + IN IAFWDramConfig *DramConfigData, + IN UINTN *MrcTrainingDataAddr, + IN UINTN *MrcBootDataAddr, + IN UINT8 BoardId + ) +{ + DRAM_POLICY_PPI *DramPolicy; + SYSTEM_CONFIGURATION SystemConfiguration; + UINTN VariableSize; + EFI_STATUS Status; + DRP_DRAM_POLICY *DrpPtr; + UINT8 (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]; + PlatfromDramConf *DramConfig; + BOOLEAN ReadSetupVars; + + DEBUG ((EFI_D_INFO, "*** Minnow Board 3 Next DramCreatePolicyDefaults\n")); + DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI)); + if (DramPolicy == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + ReadSetupVars = FALSE; + DrpPtr = NULL; + ChSwizlePtr = NULL; + DramConfig = NULL; + + VariableSize = sizeof (SYSTEM_CONFIGURATION); + Status = VariablePpi->GetVariable ( + VariablePpi, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + +#if !(ONLY_USE_SMIP_DRAM_POLICY == 1) + Status = EFI_UNSUPPORTED; +#endif + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n")); + ReadSetupVars = TRUE; + DramPolicy->ChannelHashMask = SystemConfiguration.ChannelHashMask; + DramPolicy->SliceHashMask = SystemConfiguration.SliceHashMask; + DramPolicy->ChannelsSlicesEnabled = SystemConfiguration.ChannelsSlicesEnabled; + DramPolicy->ScramblerSupport = SystemConfiguration.ScramblerSupport; + DramPolicy->InterleavedMode = SystemConfiguration.InterleavedMode; + DramPolicy->MinRefRate2xEnabled = SystemConfiguration.MinRefRate2xEnabled; + DramPolicy->DualRankSupportEnabled = SystemConfiguration.DualRankSupportEnabled; + } + + DramConfig = &(DramConfigData->PlatformDram4); + + DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData->Platform_override)); + switch (DramConfigData->Platform_override) { + case 0: + DramConfig = &(DramConfigData->PlatformDram0); + break; + case 1: + DramConfig = &(DramConfigData->PlatformDram1); + break; + case 2: + DramConfig = &(DramConfigData->PlatformDram2); + break; + case 3: + DramConfig = &(DramConfigData->PlatformDram3); + break; + case 4: + DramConfig = &(DramConfigData->PlatformDram4); + break; + default: + // + // Do nothing if the override value does not exist. 0xFF is the + // default Platform_override value when no override is selected + // + break; + } + + DramPolicy->Package = DramConfig->Package; + DramPolicy->Profile = DramConfig->Profile; + DramPolicy->MemoryDown = DramConfig->MemoryDown; + DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize; + DramPolicy->DDR3LASR = DramConfig->DDR3LASR; + DramPolicy->SystemMemorySizeLimit = DramConfig->MemorySizeLimit; + DramPolicy->SpdAddress[0] = DramConfig->SpdAddress0; + DramPolicy->SpdAddress[1] = DramConfig->SpdAddress1; + DramPolicy->DDR3LPageSize = DramConfig->DDR3LPageSize; + DramPolicy->DDR3LASR = DramConfig->DDR3LASR; + DramPolicy->HighMemMaxVal = DramConfig->HighMemMaxVal; + DramPolicy->LowMemMaxVal = DramConfig->LowMemMaxVal; + DramPolicy->DisableFastBoot = DramConfig->DisableFastBoot; + DramPolicy->RmtMode = DramConfig->RmtMode; + DramPolicy->RmtCheckRun = DramConfig->RmtCheckRun; + DramPolicy->RmtMarginCheckScaleHighThreshold = DramConfig->RmtMarginCheckScaleHighThreshold; + + DramPolicy->MsgLevelMask = DramConfigData->Message_level_mask; + DrpPtr = (DRP_DRAM_POLICY *) (&(DramConfig->Ch0RankEnabled)); + ChSwizlePtr = (UINT8(*)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzling)); + + if (!ReadSetupVars) { + DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n")); + DramPolicy->ChannelHashMask = DramConfig->ChannelHashMask; + DramPolicy->SliceHashMask = DramConfig->SliceHashMask; + DramPolicy->ChannelsSlicesEnabled = DramConfig->ChannelsSlicesEnabled; + DramPolicy->ScramblerSupport = DramConfig->ScramblerSupport; + DramPolicy->InterleavedMode = DramConfig->InterleavedMode; + DramPolicy->MinRefRate2xEnabled = DramConfig->MinRefRate2xEnabled; + DramPolicy->DualRankSupportEnabled = DramConfig->DualRankSupportEnabled; + } + + // + // DRP + // + if (DrpPtr != NULL) { + CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp)); + } + + // + // Swizzling + // + if (ChSwizlePtr != NULL) { + CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle)); + } + + if (ReadSetupVars) { + if (SystemConfiguration.Max2G == 0) { + DramPolicy->SystemMemorySizeLimit = 0x800; + } + } + + DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr; + DramPolicy->MrcBootDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr; + + *DramPolicyPpi = DramPolicy; + + return EFI_SUCCESS; +} + +/** + BgUpdatePcieConfig updates the PCIe config block for platform specific items. + + @param[in] PciePreMemConfig The pointer to the PCIe premem config instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +Mb3NUpdatePcieConfig ( + IN SC_PCIE_PREMEM_CONFIG *PciePreMemConfig + ) +{ + // + // Minnow Board v3 Next + // + PciePreMemConfig->RootPort[0].Perst = W_PMU_PLTRST_B; // D20:F0 - PCIe-A + PciePreMemConfig->RootPort[1].Perst = W_PMU_PLTRST_B; // D20:F1 - PCIe-B + PciePreMemConfig->RootPort[2].Perst = W_PMU_PLTRST_B; // D19:F0 - PCIe-C + PciePreMemConfig->RootPort[3].Perst = W_PMU_PLTRST_B; // D19:F1 - PCIe-D + PciePreMemConfig->RootPort[4].Perst = W_PMU_PLTRST_B; // D19:F2 - LAN + PciePreMemConfig->RootPort[5].Perst = W_PMU_PLTRST_B; // D19:F3 - Empty + PciePreMemConfig->RootPort[0].Clock = W_GPIO_210; // D20:F0 - PCIe-A + PciePreMemConfig->RootPort[1].Clock = W_GPIO_211; // D20:F1 - PCIe-B + PciePreMemConfig->RootPort[2].Clock = W_GPIO_212; // D19:F0 - PCIe-C + PciePreMemConfig->RootPort[3].Clock = 0; // D19:F1 - PCIe-D + PciePreMemConfig->RootPort[4].Clock = W_GPIO_209; // D19:F2 - LAN + PciePreMemConfig->RootPort[5].Clock = 0; // D19:F3 - Empty + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.h new file mode 100644 index 000000000..663ab6f50 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitMiscs.h @@ -0,0 +1,67 @@ +/** @file + Multiplatform initialization header file. + This file includes package header files, library classes. + + Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MINNOW_NEXT_MULTIPLATFORM_LIB_H_ +#define _MINNOW_NEXT_MULTIPLATFORM_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include "PlatformId.h" +#include "MmrcData.h" + + +extern UPDATE_FSPM_UPD_FUNC mMb3NUpdateFspmUpdPtr; +extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3NDramCreatePolicyDefaultsPtr; +extern UPDATE_PCIE_CONFIG_FUNC mMb3NUpdatePcieConfigPtr; + +typedef struct { + UINT8 DeviceWidth[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 DramDensity[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 Option[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 RankEnable[DRAM_POLICY_NUMBER_CHANNELS]; + CHAR8 DescString[32]; +} BOARD_CHANNEL_INFO; + +EFI_STATUS +EFIAPI +Mb3NUpdateFspmUpd ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN FSPM_UPD *FspUpdRgn + ); + +EFI_STATUS +EFIAPI +Mb3NDramCreatePolicyDefaults ( + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi, + OUT DRAM_POLICY_PPI **DramPolicyPpi, + IN IAFWDramConfig *DramConfigData, + IN UINTN *MrcTrainingDataAddr, + IN UINTN *MrcBootDataAddr, + IN UINT8 BoardId + ); + +EFI_STATUS +EFIAPI +Mb3NUpdatePcieConfig ( + IN SC_PCIE_PREMEM_CONFIG *PciePreMemConfig + ); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf new file mode 100644 index 000000000..6cb3dcfa5 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/BoardInitPreMem.inf @@ -0,0 +1,62 @@ +## @file +# Board detected module for Intel(R) Atom(TM) x5 Processor Series. +# It will detect the board ID. +# +# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = MinnowBoard3NextInitPreMem + FILE_GUID = A40B6929-FF79-4CF4-8B4E-40554390EC71 + VERSION_STRING = 1.0 + MODULE_TYPE = PEIM + CONSTRUCTOR = MinnowBoard3NextInitConstructor + +[Sources] + BoardInit.c + PlatformId.c + BoardInitMiscs.c + +[LibraryClasses] + PeiServicesLib + PcdLib + MmPciLib + IoLib + +[Packages] + MdePkg/MdePkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonFspPkg/BroxtonFspPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec + +[Pcd] + gPlatformModuleTokenSpaceGuid.PcdBoardId + gPlatformModuleTokenSpaceGuid.PcdFabId + gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc + gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc + gPlatformModuleTokenSpaceGuid.PcdUpdatePcieConfigFunc + gMinnowModuleTokenSpaceGuid.PcdDefaultFabId ## CONSUMES + gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES + gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSerialIoUartNumber + +[Guids] + +[Ppis] + gBoardPreMemInitPpiGuid + gBoardPreMemInitDoneGuid + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.c new file mode 100644 index 000000000..c1ed7fc78 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.c @@ -0,0 +1,231 @@ +/** @file + Implement Platform ID code. + + Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include "PlatformId.h" + +PAD_ID_INFO gRawBoardIdPadInfo[] = { + {NW_PMIC_STDBY, EnPd, P_20K_L}, + {NW_GPIO_213, EnPd, P_20K_L}, + {NW_PMIC_RESET_B, EnPd, P_20K_L}, + {NW_PMIC_PWRGOOD, EnPd, P_20K_L}, + {N_GPIO_27, EnPd, P_20K_L}, + {N_GPIO_72, EnPd, P_20K_L}, + {N_GPIO_64, EnPd, P_20K_L} +}; + +// +// MinnowBoardv3 = 0x00000017 +//=========================================== +// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1 +// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1 +// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 +// NW_PMIC_PWRGOOD - - 10k PD -> 0 +// N_GPIO_27 - BOARD_ID3 - 10k PU -> 1 +// N_GPIO_72 - - Float -> 0 +// N_GPIO_64 - - Float -> 0 +//=========================================== + +// Benson Glacier = 0x00000024 +//=========================================== +// NW_PMIC_STDBY - BOARD_ID0 - 10k PD -> 0 +// NW_GPIO_213 - BOARD_ID1 - 10k PD -> 0 +// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 +// NW_PMIC_PWRGOOD - - Float -> 0 +// N_GPIO_27 - - Float -> 0 +// N_GPIO_72 - BOARD_ID3 - 10k PU -> 1 +// N_GPIO_64 - - Float -> 0 +//=========================================== + +// MinnowBoardv3Next = 0x00000040 +//=========================================== +// NW_PMIC_STDBY - - Float -> 0 +// NW_GPIO_213 - - Float -> 0 +// NW_PMIC_RESET_B - - Float -> 0 +// NW_PMIC_PWRGOOD - - Float -> 0 +// N_GPIO_27 - - Float -> 0 +// N_GPIO_72 - - Float -> 0 +// N_GPIO_64 - - 10k PU -> 1 +//=========================================== + +// LeafHill = 0x00000047 +//=========================================== +// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1 +// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1 +// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 +// NW_PMIC_PWRGOOD - BOARD_ID3 - 10k PD -> 0 +// N_GPIO_27 - - Float -> 0 +// N_GPIO_72 - - Float -> 0 +// N_GPIO_64 - - 0k PU -> 1 +//=========================================== + +BOARD_ID_INFO gBoardIdInfo[] = { + {0x00000017, BOARD_ID_MINNOW}, // MinnowBoardv3 + {0x00000024, BOARD_ID_BENSON}, // Benson Glacier + {0x00000040, BOARD_ID_MINNOW_NEXT}, // MinnowBoardv3Next + {0x00000047, BOARD_ID_LFH_CRB} // LeafHill +}; + +PAD_ID_INFO gMb3nHwconfPadInfo[] = { + {W_GPIO_128, DisPuPd, P_NONE}, // HWCONF0 + {W_GPIO_131, DisPuPd, P_NONE}, // HWCONF1 + {W_GPIO_130, DisPuPd, P_NONE}, // HWCONF2 + {W_GPIO_129, DisPuPd, P_NONE}, // HWCONF3 + {W_GPIO_139, DisPuPd, P_NONE}, // HWCONF4 + {W_GPIO_138, DisPuPd, P_NONE}, // HWCONF5 + {NW_GPIO_80, DisPuPd, P_NONE}, // HWCONF6 + {NW_GPIO_81, DisPuPd, P_NONE}, // HWCONF7 + {NW_GPIO_83, DisPuPd, P_NONE} // HWCONF8 +}; + +UINT32 +EFIAPI +GetId ( + IN PAD_ID_INFO *PadInfoPtr, + IN UINT8 NumberOfEntries + ) +{ + UINT8 bit; + UINT32 CommAndOffset; + UINT8 index; + BXT_CONF_PAD0 padConfg0; + BXT_CONF_PAD0 padConfg0Org; + BXT_CONF_PAD1 padConfg1; + BXT_CONF_PAD1 padConfg1Org; + UINT32 ReturnId; + + // + // Get ID from PAD + // + if ((PadInfoPtr == NULL) || (NumberOfEntries == 0)) { + // + // Nothing in structure. Skip. + // + ReturnId = 0xFF; + } else { + ReturnId = 0; + for (index = 0; index < NumberOfEntries; index++) { + CommAndOffset = PadInfoPtr[index].CommAndOffset; + padConfg0Org.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET); + padConfg1Org.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET); + // + // Set pad to be able to read the bit + // + padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET); + padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET); + padConfg0.r.PMode = M0; // Set to GPIO mode + padConfg0.r.GPIORxTxDis = GPI; // Set to GPI + padConfg1.r.IOSTerm = PadInfoPtr[index].IOSTerm; // Enable pull-up/down + padConfg1.r.Term = PadInfoPtr[index].Term; // Set pull-up/down value + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0); + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1); + // + // Read the bit + // + bit = (UINT8) (((GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << index); + ReturnId |= bit; + // + // Restore orginal pad programming. + // + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0Org.padCnf0); + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1Org.padCnf1); + } + } + return ReturnId; +} + +UINT8 +EFIAPI +GetCommonBoardId ( + VOID + ) +{ + UINT8 BoardId; + UINT8 index; + UINT32 RawBoardId; + + DEBUG ((DEBUG_INFO, "%a(#%3d) - Starting...\n", __FUNCTION__, __LINE__)); + + // + // Get BoardId + // + RawBoardId = GetId (gRawBoardIdPadInfo, sizeof (gRawBoardIdPadInfo) / sizeof (gRawBoardIdPadInfo[0])); + + // + // Convert from a 32-bit raw BoardId to an 8-bit one. + // + BoardId = BOARD_ID_APL_UNKNOWN; + for (index = 0; index < sizeof (gBoardIdInfo) / sizeof (gBoardIdInfo[0]); index++) { + if (gBoardIdInfo[index].RawId == RawBoardId) { + BoardId = gBoardIdInfo[index].BoardId; + break; + } + } + + DEBUG ((DEBUG_INFO, "%a(#%3d) - BoardId: %02X\n", __FUNCTION__, __LINE__, BoardId)); + return BoardId; +} + + + +EFI_STATUS +EFIAPI +Minnow3NextGetEmbeddedBoardIdFabId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BoardId, + OUT UINT8 *FabId + ) +{ + DEBUG ((DEBUG_INFO, "%a(#%3d) - Starting...\n", __FUNCTION__, __LINE__)); + + // + // Get BoardId + // + *BoardId = GetCommonBoardId (); + + if (*BoardId != BOARD_ID_MINNOW_NEXT) { + *BoardId = BOARD_ID_APL_UNKNOWN; + *FabId = UNKNOWN_FAB; + } else { + // + // Get FabId + // + *FabId = FAB_ID_A; // MBv3N FabID is behind the EC. Just say Fab A for now. + DEBUG ((DEBUG_INFO, "%a(#%3d) - FabId : %02X\n", __FUNCTION__, __LINE__, *FabId)); + } + + return EFI_SUCCESS; +} + +UINT32 +EFIAPI +Minnow3NextGetHwconfStraps ( + VOID + ) +{ + UINT32 HwconfStraps; + + // + // Get HWCONF straps + // + HwconfStraps = GetId (gMb3nHwconfPadInfo, sizeof (gMb3nHwconfPadInfo) / sizeof (gMb3nHwconfPadInfo[0])); + + return HwconfStraps; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.h new file mode 100644 index 000000000..7ee6777f3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Next/BoardInitPreMem/PlatformId.h @@ -0,0 +1,45 @@ +/** @file + Header file for the Platform ID code. + + Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __MINNOWBOARD_NEXT_PLATFORM_ID_H__ +#define __MINNOWBOARD_NEXT_PLATFORM_ID_H__ + +typedef struct { + UINT32 CommAndOffset; + UINT8 IOSTerm; + UINT8 Term; +} PAD_ID_INFO; + +typedef struct { + UINT32 RawId; + UINT8 BoardId; +} BOARD_ID_INFO; + +EFI_STATUS +EFIAPI +Minnow3NextGetEmbeddedBoardIdFabId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BoardId, + OUT UINT8 *FabId + ); + +UINT32 +EFIAPI +Minnow3NextGetHwconfStraps ( + VOID + ); + +#endif + -- 2.14.1.windows.1