From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4442021A10969 for ; Sat, 25 Nov 2017 04:19:18 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id 11so19042338wrb.6 for ; Sat, 25 Nov 2017 04:23:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=9+HEQdu8+ebbpPL9QtXYWxmiyMTypst2PRpB/3hpw6E=; b=gK3ALwgY919leOeBaBp4tg9bqk/W+tNMhZ9YimaJHwH7LS/E25drtz1xhq6yfv7JGB Yf7U/N1kqqbsdZl7h6GqRVfJBg4akWcAtniEhCIBuhFRKo9jDrRbXgWIkOG+l6EAPi/l lpuzfeZCAAljnA4cyuuvPU7Vo/2NEbwppPJII= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=9+HEQdu8+ebbpPL9QtXYWxmiyMTypst2PRpB/3hpw6E=; b=bYo4d+KNznuhNU+5aDJGICfQmvtLO/EBcB0klcZLktvJmZ3Kff0x1fniF4HywohM/x vdHsojd0sz//VrhT89+rUO/mMK9soWx6Ph7zhOPzCoXseImBQDpeqANf+ij+OlsxK3ZV /vQZd2yP99lgMZw+GZ393EELJEiBzJv1RBEXEW0f9b+A/t9HBQ1zUcwiyw4OIF3GH1CD vsEK2qMHUTMErahHhCabBwg1UPrNUK+F+J0XMZvL4M+FdNhgirNTX7PWns0vePgTzahV Fw+rKYfLOq8B0zbsc7reXN6z6DUeun4jpLHWQ1PBCjnLpu9kMtOuwEmfgUwBbewqbb6k MXrQ== X-Gm-Message-State: AJaThX62dxjwWzZ4xkRzOa5nhZbFeWFcOzxWGC+L/aGAZXpecqTMLQbJ bc0mbwQRqxt2TssyH0MZU4EhsOwrHas= X-Google-Smtp-Source: AGs4zMb/SBKeKrDgnJaL/n13v3faIJKViRxhPZXRgUoHhrVvzKwQ/pL9gElxlB6us/49EKzfiso+7w== X-Received: by 10.223.169.68 with SMTP id u62mr25814389wrc.30.1511612616392; Sat, 25 Nov 2017 04:23:36 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m133sm16837458wmd.40.2017.11.25.04.23.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 Nov 2017 04:23:35 -0800 (PST) Date: Sat, 25 Nov 2017 12:23:33 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171125122333.d2uzog5aefjcudij@bivouac.eciton.net> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171117190423.19511-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v5 0/6] add remaining support for Socionext SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 25 Nov 2017 12:19:18 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Nov 17, 2017 at 07:04:17PM +0000, Ard Biesheuvel wrote: > These are the remaining patches that still need review after the majority > of the Socionext SynQuacer support patches were merged. All remaining patches in series: Reviewed-by: Leif Lindholm > Changes since v4: > - minor changes, please see the notes in the individual patches > > Changes since v3: > - remove ACPI support for now, we can add it on top if we manage to sort > out all the SoC quirks that make it difficult to have full support under > ACPI > - add RTC support to DeveloperBox > - add eMMC support to SynQuacerEvalBoard > - incorporate review feedback on the SPI NOR driver (which was possible > after noticing that I did in fact have a manual for this IP) > - map NOR and EEPROM as writeback cacheable non-shareable; this allows the > split FV hack to be reverted, and improves boot time considerably > - some other minor changes have been applied, these have been added to the > individual patches as notes > > Changes since v2: > - converted NETSEC driver to UEFI driver model > - added a platform DXE driver that declares the non-discoverable NETSEC > device for the UEFI driver model driver to bind to > - remove hardcoded DRAM information - everything is now retrieved from > ARM Trusted Firmware > - added DT descriptions of the GPIO and interrupt controller IP blocks > - addressed various style issues and merge errors highlighted by Leif > > Ard Biesheuvel (6): > Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch > Silicon/SynQuacer: add DT description of the SDHCI controller > Silicon/Socionext: implement I2C master protocol for SynQuacer I2C > Silicon/NXP: add RTC support library for PCF8563 I2C IP > Platform/DeveloperBox: wire up RTC support > Platform/SynQuacerEvalBoard: add eMMC driver stack > > Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 13 +- > Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 6 + > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 12 + > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 8 + > Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 402 +++++++++++++ > Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 31 ++ > Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 52 ++ > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 27 + > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 4 + > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 201 +++++++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 88 ++- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 11 +- > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c | 185 ++++++ > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c | 238 ++++++++ > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 588 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h | 162 ++++++ > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 59 ++ > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 8 + > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 + > Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 30 +- > Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 + > Silicon/Socionext/SynQuacer/SynQuacer.dec | 8 + > 23 files changed, 2160 insertions(+), 20 deletions(-) > create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c > create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec > create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf > > -- > 2.11.0 >