From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9E2472034A76E for ; Tue, 28 Nov 2017 05:45:32 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id b189so2026866wmd.5 for ; Tue, 28 Nov 2017 05:49:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=06srXZRNivORj7CHURmcLFbt6G15ZOgsCk4CGWTj8Yo=; b=L1LVbcysOewSzUGUb75aNbEv4pZIrmFusK8/dhz0elv8xJwdpO3mTsTGbY5SIALtm7 zHicG38EVHR5g2aRKNrIo2OeWFsaTwGsjawtUnqqOeIeJ7A5u7KUkPbpHBOm21JK+99U x238JEZYk8QJIKgFXXILlRcP36tL0tjYE8gIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=06srXZRNivORj7CHURmcLFbt6G15ZOgsCk4CGWTj8Yo=; b=cCWL5GUZTpxIYXgZ4q4pac3MsCTyc5JFEzDfx44jGfVGpzNiNbXA60uwV8iyNhr2JR X9Ct1duXnPJJY/XnoFNqM538wQ7c1RdmKFQj7kr+p7RMcf4AnNcL7fu9PhqoNcFwjnm3 CGgEhzdnB2+tZ339Z3VIWzn3TnikoqFuE3Z4Oh8g0e3hsMQxIphXEq7sLGNlr0ey7g73 8SaWpi2RV42Dwv35rU3S74LWupDDo7vLHSPtZY1x6GkV4pU0Tww34HLxTlCBPA/zRdIA q1/JmgzJu+mKGDLVzvxAnwhNXDZd2JiN9lqQ1GRff9dXns0SumJicHKX7eZB1BvLw1tx eWHw== X-Gm-Message-State: AJaThX6fRHfV0itCya2agp9afcysmETI2V3kCqNIe3oUWJIX+LJ+ub6l uRZJeEm3hioxB/iW4Lo6eUA9Jw== X-Google-Smtp-Source: AGs4zMbYiuaWVbETHMZ5lXTgFH5/OYaefYM95VqulDwhNdJAky+QRn9kVgpm0ILanbxp75bUE6TOmw== X-Received: by 10.28.113.84 with SMTP id m81mr21557367wmc.134.1511876994118; Tue, 28 Nov 2017 05:49:54 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v16sm3796262wrb.11.2017.11.28.05.49.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Nov 2017 05:49:53 -0800 (PST) Date: Tue, 28 Nov 2017 13:49:51 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Daniel Thompson , masahisa.kojima@socionext.com, =?utf-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= Message-ID: <20171128134951.ah5rkkes5wx6leu6@bivouac.eciton.net> References: <20171128132807.16701-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2017 13:45:33 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Nov 28, 2017 at 01:37:20PM +0000, Ard Biesheuvel wrote: > On 28 November 2017 at 13:28, Ard Biesheuvel wrote: > > As it turns out, it is surprisingly easy to configure both the NETSEC > > and eMMC devices as cache coherent for DMA, given that they are both > > behind the same SMMU which is already configured in passthrough mode. Configures in passthrough mode by edk2 or earlier firmware? > > So update the static SMMU configuration to make memory accesses performed > > by these devices inner shareable, inner/outer writeback cacheable, which > > makes them cache coherent with the CPUs. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > --- > > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- > > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ > > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- > > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ > > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ > > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ > > 6 files changed, 34 insertions(+), 2 deletions(-) > > > > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > > index 7245240012bc..dd4a7f9baf69 100644 > > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > > @@ -597,7 +597,7 @@ [Components.common] > > NetworkPkg/HttpBootDxe/HttpBootDxe.inf > > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { > > > > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf > > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf > > } > > > > # > > Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well. Do I wait for a v2 including that? / Leif > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > index 7c791de213c7..c9fee5d1f350 100644 > > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > @@ -456,6 +456,7 @@ > > max-speed = <1000>; > > max-frame-size = <9000>; > > phy-handle = <ðphy0>; > > + dma-coherent; > > > > #address-cells = <1>; > > #size-cells = <0>; > > @@ -557,6 +558,7 @@ > > fujitsu,cmd-dat-delay-select; > > clocks = <&clk_alw_c_0 &clk_alw_b_0>; > > clock-names = "core", "iface"; > > + dma-coherent; > > status = "disabled"; > > }; > > }; > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > > index 9b1957e99907..1c38b3706f9d 100644 > > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > > @@ -185,7 +185,7 @@ RegisterEmmc ( > > > > Status = RegisterNonDiscoverableMmioDevice ( > > NonDiscoverableDeviceTypeSdhci, > > - NonDiscoverableDeviceDmaTypeNonCoherent, > > + NonDiscoverableDeviceDmaTypeCoherent, > > NULL, > > &mSdMmcControllerHandle, > > 1, > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > > index b28d05650bb5..acb3e0272d3f 100644 > > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > > @@ -181,6 +181,27 @@ I2cEnumerate ( > > return EFI_SUCCESS; > > } > > > > +#define SMMU_SCR0 0x0 > > +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22) > > +#define SMMU_SCR0_MTCFG (0x1 << 20) > > +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16) > > + > > +STATIC > > +VOID > > +SmmuEnableCoherentDma ( > > + VOID > > + ) > > +{ > > + // > > + // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and > > + // is configured in passthrough mode by default. Let's set the global memory > > + // type override as well, so that all memory accesses by these devices are > > + // inner shareable inner/outer writeback cacheable. > > + // > > + MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0, > > + SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB); > > +} > > + > > STATIC > > EFI_STATUS > > EFIAPI > > @@ -272,5 +293,7 @@ PlatformDxeEntryPoint ( > > NULL); > > ASSERT_EFI_ERROR (Status); > > > > + SmmuEnableCoherentDma (); > > + > > return EFI_SUCCESS; > > } > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > index 3c7bd58866cc..f43adcc8607f 100644 > > --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > @@ -65,4 +65,8 @@ > > #define SYNQUACER_PCIE_BASE 0x58200000 > > #define SYNQUACER_PCIE_SIZE 0x00200000 > > > > +// SCB SMMU > > +#define SYNQUACER_SCB_SMMU_BASE 0x52E00000 > > +#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB > > + > > #endif > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > > index a640b3e0c0d1..1402ecafce4a 100644 > > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > > @@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { > > FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)), > > ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase), > > FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)), > > + > > + // NETSEC/eMMC SMMU > > + ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE), > > }; > > > > STATIC > > -- > > 2.11.0 > >