From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
"Daniel Thompson" <daniel.thompson@linaro.org>,
masahisa.kojima@socionext.com,
"Pipat/メタワニットポン ピパット" <methavanitpong.pipat@socionext.com>
Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC
Date: Tue, 28 Nov 2017 14:19:54 +0000 [thread overview]
Message-ID: <20171128141954.6drhx3avq7hwlch2@bivouac.eciton.net> (raw)
In-Reply-To: <CAKv+Gu-hzKXuZLG-E0viK8VgczwbEmh9UZ1iGjrU1oZONF8XzA@mail.gmail.com>
On Tue, Nov 28, 2017 at 01:53:49PM +0000, Ard Biesheuvel wrote:
> On 28 November 2017 at 13:49, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > On Tue, Nov 28, 2017 at 01:37:20PM +0000, Ard Biesheuvel wrote:
> >> On 28 November 2017 at 13:28, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> >> > As it turns out, it is surprisingly easy to configure both the NETSEC
> >> > and eMMC devices as cache coherent for DMA, given that they are both
> >> > behind the same SMMU which is already configured in passthrough mode.
> >
> > Configures in passthrough mode by edk2 or earlier firmware?
>
> No, it is the CM3 firmware that configures the various SMMUs on this platform.
Right, could you add that to the above statement please?
"... already configured in passthrough mode by the CM3 firmware."?
> >> > So update the static SMMU configuration to make memory accesses performed
> >> > by these devices inner shareable, inner/outer writeback cacheable, which
> >> > makes them cache coherent with the CPUs.
> >> >
> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> > ---
> >> > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +-
> >> > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++
> >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +-
> >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++
> >> > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++
> >> > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++
> >> > 6 files changed, 34 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> >> > index 7245240012bc..dd4a7f9baf69 100644
> >> > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> >> > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> >> > @@ -597,7 +597,7 @@ [Components.common]
> >> > NetworkPkg/HttpBootDxe/HttpBootDxe.inf
> >> > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
> >> > <LibraryClasses>
> >> > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> >> > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf
> >> > }
> >> >
> >> > #
> >>
> >> Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well.
> >
> > Do I wait for a v2 including that?
> >
>
> Would you like me to?
No, I was just wondering.
Does the .dtsi change not cause issues for DeveloperBox without it?
> I added this for Daniel and/or Masami, in case they were intending to
> test this patch. I'd like to get confirmation from them or others that
> this works as expected before merging this, so there is no rush.
Right, thanks.
/
Leif
next prev parent reply other threads:[~2017-11-28 14:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-28 13:28 [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC Ard Biesheuvel
2017-11-28 13:37 ` Ard Biesheuvel
2017-11-28 13:49 ` Leif Lindholm
2017-11-28 13:53 ` Ard Biesheuvel
2017-11-28 14:19 ` Leif Lindholm [this message]
2017-11-28 14:22 ` Ard Biesheuvel
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