From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 49CAA203564B2 for ; Tue, 28 Nov 2017 06:15:35 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id q9so145309wre.7 for ; Tue, 28 Nov 2017 06:19:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0opi+Pu0xxJHlhcz+QbHAHqpqKIx8SggO6yCIRphUpg=; b=FqWnoqYRvmsOdNfoHFkGwt6ZjXvAqniwjrwVmB9iThyFNtgWp+SPfn8onQQXKB7Bzi tyQ4q5B/eweULSGU92FHrSSlwl8BzZpyr4iw/9QOghNir9jyUjiij6yAAc3ObNUkwN9P YGNLRl79aywXpcEqMGre78EGJXT/uImT+BBf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0opi+Pu0xxJHlhcz+QbHAHqpqKIx8SggO6yCIRphUpg=; b=WTwZnqpJGqw3zvVQq57DFo3rKg7FxJO/Zkgayv0GSd3ohuvKKDTj2tiaL/D4g+D5vy UUKTvDOBjF5M75FEdEQ3XdoDQiw2mBjuqiqgEhmEcOdoJjIOr1EKEBNVaYzxJU+XIRCj Fyj8qeSwNZBXPVJ97uKRSfiUOg49mpZGnjYc0vEduya7udo6oKj1IB3lUfWFjqsbt6pm AhpehZ7fr2TVtoC0Mhf2qov2IBsveZ3Ev5NHUoUTkyxeCFnV2En/o16c7FXnqs+6L7mC fLUjFvTAjJp0/+n5t52lri0bIodd22Q6/L1uDzNqKv8W4diT6bDu0X1/1tFtsGvDGzap csjA== X-Gm-Message-State: AJaThX6fIZvfoB5cLDuq4EqHUBnQBlQzwm4HAb21J4HuNjpsErYS3GYx SlT1KnxKrOhI4kqwa84HgYQ6HQ== X-Google-Smtp-Source: AGs4zMZp1NIrqEPhuEttlVhe/cO8CztEWb5GFP+mUJrGUpQ8zisv/vpMkAc0ZlgEf3YKTtuTMIptFQ== X-Received: by 10.223.200.133 with SMTP id k5mr11397434wrh.79.1511878797381; Tue, 28 Nov 2017 06:19:57 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 19sm22824029wmn.15.2017.11.28.06.19.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Nov 2017 06:19:56 -0800 (PST) Date: Tue, 28 Nov 2017 14:19:54 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Daniel Thompson , masahisa.kojima@socionext.com, =?utf-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= Message-ID: <20171128141954.6drhx3avq7hwlch2@bivouac.eciton.net> References: <20171128132807.16701-1-ard.biesheuvel@linaro.org> <20171128134951.ah5rkkes5wx6leu6@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2017 14:15:36 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Nov 28, 2017 at 01:53:49PM +0000, Ard Biesheuvel wrote: > On 28 November 2017 at 13:49, Leif Lindholm wrote: > > On Tue, Nov 28, 2017 at 01:37:20PM +0000, Ard Biesheuvel wrote: > >> On 28 November 2017 at 13:28, Ard Biesheuvel wrote: > >> > As it turns out, it is surprisingly easy to configure both the NETSEC > >> > and eMMC devices as cache coherent for DMA, given that they are both > >> > behind the same SMMU which is already configured in passthrough mode. > > > > Configures in passthrough mode by edk2 or earlier firmware? > > No, it is the CM3 firmware that configures the various SMMUs on this platform. Right, could you add that to the above statement please? "... already configured in passthrough mode by the CM3 firmware."? > >> > So update the static SMMU configuration to make memory accesses performed > >> > by these devices inner shareable, inner/outer writeback cacheable, which > >> > makes them cache coherent with the CPUs. > >> > > >> > Contributed-under: TianoCore Contribution Agreement 1.1 > >> > Signed-off-by: Ard Biesheuvel > >> > --- > >> > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- > >> > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ > >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- > >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ > >> > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ > >> > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ > >> > 6 files changed, 34 insertions(+), 2 deletions(-) > >> > > >> > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > >> > index 7245240012bc..dd4a7f9baf69 100644 > >> > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > >> > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > >> > @@ -597,7 +597,7 @@ [Components.common] > >> > NetworkPkg/HttpBootDxe/HttpBootDxe.inf > >> > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { > >> > > >> > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf > >> > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf > >> > } > >> > > >> > # > >> > >> Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well. > > > > Do I wait for a v2 including that? > > > > Would you like me to? No, I was just wondering. Does the .dtsi change not cause issues for DeveloperBox without it? > I added this for Daniel and/or Masami, in case they were intending to > test this patch. I'd like to get confirmation from them or others that > this works as expected before merging this, so there is no rush. Right, thanks. / Leif