From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4F6A721B00DC4 for ; Wed, 29 Nov 2017 10:30:50 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id f140so7870127wmd.2 for ; Wed, 29 Nov 2017 10:35:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=EUeDvCDQoK4SpXuaD/Z7x00GeW0FWTEDD0SKYW+xcRA=; b=GmBxMuaIJmJzeMfiKDJOUXgoqyBUXZcd5hZGvTjh4BfchKxsUjNGsmmJIlVgZBa8uC JQE38XNYiI0RPiFJpf7hfPkbUYXHNptlVohh4FWz/baOyZivSQvHTlLduxcJRxb3nsOj B7NWy8Ix6VpvKt8TskbJn+RPZ0m4Odmv247vE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=EUeDvCDQoK4SpXuaD/Z7x00GeW0FWTEDD0SKYW+xcRA=; b=YiJbw34oChlkanAjej9xSh28P4e8eNrJZH5ddI2xZGigFgXv8B+01/afla6W828ao+ oLaEdRVm39Md1GENNadggwEuqFrRncCK5lcp+bVmVqV4J6YFXU4eyHygLf/RjySxjtSL fniLQgD2P0xGYwIczjQv/hagQTuzVw7OR6PU2tVxwWcYwFjKHejLi7aCM9fJyTVcDOaH d4j/+9zksg0q9bI62pNN17XvLQS6hgz2eBY57EGvwFDd8e1srTg6IjmKaGj8Tj3QxWgA e7Pau3kuQpMqSITR0B66hbfmSrjJUDGUACajx25mRbfsOKJEs4WqHAS0AOVL/H2vk618 T0gg== X-Gm-Message-State: AJaThX6jPZ0U2zEpxXF5ksxDpm5kylJD+2NHVRf40jkuzuHNNymvQ9FJ G0HCUicb53p4lmPTwKVtLw2cIzbQyvw= X-Google-Smtp-Source: AGs4zMZD7CN5wXR4o0+3bc3gbnQzuG8+7Afrn5f8LQxnikEc0TlikOT7zUo9ETa8YXE2eFsduXYAMQ== X-Received: by 10.28.111.218 with SMTP id c87mr3158607wmi.91.1511980512533; Wed, 29 Nov 2017 10:35:12 -0800 (PST) Received: from localhost.localdomain ([105.137.43.27]) by smtp.gmail.com with ESMTPSA id l16sm6647650wma.19.2017.11.29.10.35.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Nov 2017 10:35:11 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Wed, 29 Nov 2017 18:35:05 +0000 Message-Id: <20171129183505.7954-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: fix weird indentation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Nov 2017 18:30:50 -0000 Fix the weird indentation in the various #defines in the file containing the RC init code. This is a whitespace only change. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 138 ++++++++++---------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 1bbef5b6cf98..6b42d3e29806 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -46,75 +46,75 @@ #define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C -#define CORE_CONTROL 0x000 -#define APP_LTSSM_ENABLE BIT4 -#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0) - -#define AXI_CLK_STOP 0x004 -#define DBI_ACLK_STOP BIT8 -#define SLV_ACLK_STOP BIT4 -#define MSTR_ACLK_STOP BIT0 -#define DBI_CSYSREQ_REG BIT9 -#define SLV_CSYSREQ_REG BIT5 -#define MSTR_CSYSREQ_REG BIT1 - -#define RESET_CONTROL_1 0x00C -#define PERST_N_O_REG BIT5 -#define PERST_N_I_REG BIT4 -#define BUTTON_RST_N_REG BIT1 -#define PWUP_RST_N_REG BIT0 - -#define RESET_CONTROL_2 0x010 - -#define RESET_SELECT_1 0x014 -#define SQU_RST_SEL BIT29 -#define PHY_RST_SEL BIT28 -#define PWR_RST_SEL BIT24 -#define STI_RST_SEL BIT20 -#define N_STI_RST_SEL BIT16 -#define CORE_RST_SEL BIT12 -#define PERST_SEL BIT4 -#define BUTTON_RST_SEL BIT1 -#define PWUP_RST_SEL BIT0 - -#define RESET_SELECT_2 0x018 -#define DBI_ARST_SEL BIT8 -#define SLV_ARST_SEL BIT4 -#define MSTR_ARST_SEL BIT0 - -#define EM_CONTROL 0x030 -#define PRE_DET_STT_REG BIT4 - -#define EM_SELECT 0x034 -#define PRE_DET_STT_SEL BIT4 - -#define PM_CONTROL_2 0x050 -#define SYS_AUX_PWR_DET BIT8 - -#define PHY_CONFIG_COM_6 0x114 -#define PIPE_PORT_SEL (BIT1 | BIT0) - -#define LINK_MONITOR 0x210 -#define SMLH_LINK_UP BIT0 - -#define LINK_CAPABILITIES_REG 0x07C -#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4) -#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0) - -#define LINK_CONTROL_LINK_STATUS_REG 0x080 -#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20) -#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16) - -#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 -#define BASE_CLASS_CODE 0xFF000000 -#define BASE_CLASS_CODE_VALUE 0x06 -#define SUBCLASS_CODE 0x00FF0000 -#define SUBCLASS_CODE_VALUE 0x04 -#define PROGRAM_INTERFACE 0x0000FF00 -#define PROGRAM_INTERFACE_VALUE 0x00 - -#define MISC_CONTROL_1_OFF 0x8BC -#define DBI_RO_WR_EN BIT0 +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT4 +#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT8 +#define SLV_ACLK_STOP BIT4 +#define MSTR_ACLK_STOP BIT0 +#define DBI_CSYSREQ_REG BIT9 +#define SLV_CSYSREQ_REG BIT5 +#define MSTR_CSYSREQ_REG BIT1 + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT5 +#define PERST_N_I_REG BIT4 +#define BUTTON_RST_N_REG BIT1 +#define PWUP_RST_N_REG BIT0 + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_1 0x014 +#define SQU_RST_SEL BIT29 +#define PHY_RST_SEL BIT28 +#define PWR_RST_SEL BIT24 +#define STI_RST_SEL BIT20 +#define N_STI_RST_SEL BIT16 +#define CORE_RST_SEL BIT12 +#define PERST_SEL BIT4 +#define BUTTON_RST_SEL BIT1 +#define PWUP_RST_SEL BIT0 + +#define RESET_SELECT_2 0x018 +#define DBI_ARST_SEL BIT8 +#define SLV_ARST_SEL BIT4 +#define MSTR_ARST_SEL BIT0 + +#define EM_CONTROL 0x030 +#define PRE_DET_STT_REG BIT4 + +#define EM_SELECT 0x034 +#define PRE_DET_STT_SEL BIT4 + +#define PM_CONTROL_2 0x050 +#define SYS_AUX_PWR_DET BIT8 + +#define PHY_CONFIG_COM_6 0x114 +#define PIPE_PORT_SEL (BIT1 | BIT0) + +#define LINK_MONITOR 0x210 +#define SMLH_LINK_UP BIT0 + +#define LINK_CAPABILITIES_REG 0x07C +#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4) +#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0) + +#define LINK_CONTROL_LINK_STATUS_REG 0x080 +#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20) +#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16) + +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 +#define BASE_CLASS_CODE 0xFF000000 +#define BASE_CLASS_CODE_VALUE 0x06 +#define SUBCLASS_CODE 0x00FF0000 +#define SUBCLASS_CODE_VALUE 0x04 +#define PROGRAM_INTERFACE 0x0000FF00 +#define PROGRAM_INTERFACE_VALUE 0x00 + +#define MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN BIT0 STATIC VOID -- 2.11.0