From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::230; helo=mail-wm0-x230.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3FF5221660EF for ; Wed, 29 Nov 2017 11:08:17 -0800 (PST) Received: by mail-wm0-x230.google.com with SMTP id f9so8126028wmh.0 for ; Wed, 29 Nov 2017 11:12:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=O7qjybpGCbjyIrda0AuHb1cArNKQltMIYn9Usp+URf8=; b=PBEHvDQ/IhatSo8/QEzq8x/OjN5oBl8ICTOwm8wZCkgC4quZAhw7F4D6mswKwB1DU/ ICcsrkkZueGM29QikILyt3EQ2SQODWh8gP/Sree/EvQJ189+j7/yu4rdsE1lM51Dw7UB 5o105PbqaG9di5TMDFLEvTO0ehDmONSN1FVwM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=O7qjybpGCbjyIrda0AuHb1cArNKQltMIYn9Usp+URf8=; b=FJlskodaCZBM5scIh6CgSA6U43ZIE42GnLwnf/ZM7T+b29I/Lj/paNFn+SPs0BjK0H vEPsw2j7+CKYncDX1jSeIoLoluaPmHUkzqowArClkvliDQJA9AeNm4EukFwqe6YY8V/d Vvea6dPhC4DP+b+suyQWhnHQmkguWClMHm+TbgIzxGSCLvyjcGF2LebFNew26suIXaAK 2npGLoyk08gVnlw3y6b7S4qEBuIlIH2HeKEr3dnf5AtjY+mzK+rkH/4txu7r5jXBNFmP NciFvnkAvta0LYbEJ2KnmbpC73fuJ5N+RB29N0Nq3i/20Vj8obgfSmoO4F8irG7YgIhX G5bw== X-Gm-Message-State: AJaThX4iUy/NxMw+YhBzjbGeQFGYRO0KjYYEzeI9p81xtuyHcJxuuWR7 BGLSQOutxXhR9gSjqJkLvipPjACFZ24= X-Google-Smtp-Source: AGs4zMYvHUsaK1MiIb41le1j5I8+y/NzPG8jC85KJ1pBt8bVlnpcRPJhw97KfVYoi/WeeApStHNg0w== X-Received: by 10.28.103.68 with SMTP id b65mr3547375wmc.117.1511982760796; Wed, 29 Nov 2017 11:12:40 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id p28sm42849008wmf.2.2017.11.29.11.12.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 29 Nov 2017 11:12:39 -0800 (PST) Date: Wed, 29 Nov 2017 19:12:38 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masahisa.kojima@socionext.com, methavanitpong.pipat@socionext.com, masami.hiramatsu@linaro.org Message-ID: <20171129191238.ewibi45tbkstbrnu@bivouac.eciton.net> References: <20171129184459.9017-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171129184459.9017-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Nov 2017 19:08:18 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 29, 2017 at 06:44:59PM +0000, Ard Biesheuvel wrote: > As it turns out, getting the PCIe controllers to switch to Gen2 speed > is surprisingly easy. It only involves setting the 'speed change' bit > in the controller at initialization time, after which the hardware > will automatically attempt to switch to Gen2 speed after training at > Gen1 speed has completed. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Hmm? Well, that sounds like an improvement. Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 6b42d3e29806..e63b3a4bb23b 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -113,6 +113,9 @@ > #define PROGRAM_INTERFACE 0x0000FF00 > #define PROGRAM_INTERFACE_VALUE 0x00 > > +#define GEN2_CONTROL_OFF 0x80c > +#define DIRECT_SPEED_CHANGE BIT17 > + > #define MISC_CONTROL_1_OFF 0x8BC > #define DBI_RO_WR_EN BIT0 > > @@ -295,6 +298,9 @@ PciInitController ( > EFI_PCI_COMMAND_MEMORY_SPACE | > EFI_PCI_COMMAND_BUS_MASTER); > > + // Force link speed change to Gen2 at link up > + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); > + > // Region 0: MMIO32 range > ConfigureWindow (DbiBase, 0, > RootBridge->Mem.Base, > -- > 2.11.0 >