From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFF48221660EF for ; Wed, 29 Nov 2017 11:10:31 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id l141so8527787wmg.1 for ; Wed, 29 Nov 2017 11:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=kfQE8qi3qjvled29jz4/pNdU0zbRPELC8rbkUXdjZf4=; b=Af6BcHZLp8enfmf+xS8p0ZjYXtT5t64VbTSTY5desP9BFFrxWIgNfERJIMXCTlnThj WS3qk1UlJrKeS1Ow+RuSl8KrbI9ok3BP+Jk9jAv1YVESiqjsW/fgykYmawHq3/4Scufi 01jP8rt8gj8hfqmSL5IvgO7uxhkBjefWcQj8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=kfQE8qi3qjvled29jz4/pNdU0zbRPELC8rbkUXdjZf4=; b=tOo2lex5nA65B604nlvvFpTRbt/GzVu0E3wMDMWexTL5NeM3llKs8tLvEx6C+0CBJo OnzvM27hzHobAweu+nfdsjbISG50G6htyFwKfS2ZL2Hk9vkRl1cKTLRMapoYLdYM56tn j3xdAutM9Cbh2gVUHpzUGXjCfFLb/LdBRo+MfiXbHbVDYFMcybAU3v7QT4q/rKcT8rMB xwVNB+uERnIhclsKPk+nNcOHe3vMWh3cUtd/LlatU61DF+C8uTkLdZ4HheDVNCPADxxV pPM20NR27jQA0HTuAayjmesALmi12bg78D2+jIbqROrcMtQYbat1blsXMB7S6XMC6hjJ 6Gnw== X-Gm-Message-State: AJaThX4Z+NJ4M7lzksxxdDyfOvEPxmbcCd8/H+4FcTG09jZz5zPkKfhq X/6+FqcyzT/4JaAdRalcGKacOb1/Lx8= X-Google-Smtp-Source: AGs4zMYoHer8WpMcQHIeAxCl8z1dzPG6snIyeTbztmhJfxHN+bOtnD3MTgd+V/l8ENMpyjDj+aAhpw== X-Received: by 10.28.126.87 with SMTP id z84mr1475472wmc.148.1511982894783; Wed, 29 Nov 2017 11:14:54 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m50sm4213063wrm.12.2017.11.29.11.14.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 29 Nov 2017 11:14:53 -0800 (PST) Date: Wed, 29 Nov 2017 19:14:52 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20171129191452.eg45tftys4ltny22@bivouac.eciton.net> References: <20171129183505.7954-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171129183505.7954-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: fix weird indentation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Nov 2017 19:10:32 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 29, 2017 at 06:35:05PM +0000, Ard Biesheuvel wrote: > Fix the weird indentation in the various #defines in the file containing > the RC init code. This is a whitespace only change. I did notice this when reviewing it originally, but since it was completely consistent I didn't raise any objections. > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 138 ++++++++++---------- > 1 file changed, 69 insertions(+), 69 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 1bbef5b6cf98..6b42d3e29806 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -46,75 +46,75 @@ > #define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 > #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C > > -#define CORE_CONTROL 0x000 > -#define APP_LTSSM_ENABLE BIT4 > -#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0) > - > -#define AXI_CLK_STOP 0x004 > -#define DBI_ACLK_STOP BIT8 > -#define SLV_ACLK_STOP BIT4 > -#define MSTR_ACLK_STOP BIT0 > -#define DBI_CSYSREQ_REG BIT9 > -#define SLV_CSYSREQ_REG BIT5 > -#define MSTR_CSYSREQ_REG BIT1 > - > -#define RESET_CONTROL_1 0x00C > -#define PERST_N_O_REG BIT5 > -#define PERST_N_I_REG BIT4 > -#define BUTTON_RST_N_REG BIT1 > -#define PWUP_RST_N_REG BIT0 > - > -#define RESET_CONTROL_2 0x010 > - > -#define RESET_SELECT_1 0x014 > -#define SQU_RST_SEL BIT29 > -#define PHY_RST_SEL BIT28 > -#define PWR_RST_SEL BIT24 > -#define STI_RST_SEL BIT20 > -#define N_STI_RST_SEL BIT16 > -#define CORE_RST_SEL BIT12 > -#define PERST_SEL BIT4 > -#define BUTTON_RST_SEL BIT1 > -#define PWUP_RST_SEL BIT0 > - > -#define RESET_SELECT_2 0x018 > -#define DBI_ARST_SEL BIT8 > -#define SLV_ARST_SEL BIT4 > -#define MSTR_ARST_SEL BIT0 > - > -#define EM_CONTROL 0x030 > -#define PRE_DET_STT_REG BIT4 > - > -#define EM_SELECT 0x034 > -#define PRE_DET_STT_SEL BIT4 > - > -#define PM_CONTROL_2 0x050 > -#define SYS_AUX_PWR_DET BIT8 > - > -#define PHY_CONFIG_COM_6 0x114 > -#define PIPE_PORT_SEL (BIT1 | BIT0) > - > -#define LINK_MONITOR 0x210 > -#define SMLH_LINK_UP BIT0 > - > -#define LINK_CAPABILITIES_REG 0x07C > -#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4) > -#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0) > - > -#define LINK_CONTROL_LINK_STATUS_REG 0x080 > -#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20) > -#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16) > - > -#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 > -#define BASE_CLASS_CODE 0xFF000000 > -#define BASE_CLASS_CODE_VALUE 0x06 > -#define SUBCLASS_CODE 0x00FF0000 > -#define SUBCLASS_CODE_VALUE 0x04 > -#define PROGRAM_INTERFACE 0x0000FF00 > -#define PROGRAM_INTERFACE_VALUE 0x00 > - > -#define MISC_CONTROL_1_OFF 0x8BC > -#define DBI_RO_WR_EN BIT0 > +#define CORE_CONTROL 0x000 > +#define APP_LTSSM_ENABLE BIT4 > +#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0) > + > +#define AXI_CLK_STOP 0x004 > +#define DBI_ACLK_STOP BIT8 > +#define SLV_ACLK_STOP BIT4 > +#define MSTR_ACLK_STOP BIT0 > +#define DBI_CSYSREQ_REG BIT9 > +#define SLV_CSYSREQ_REG BIT5 > +#define MSTR_CSYSREQ_REG BIT1 > + > +#define RESET_CONTROL_1 0x00C > +#define PERST_N_O_REG BIT5 > +#define PERST_N_I_REG BIT4 > +#define BUTTON_RST_N_REG BIT1 > +#define PWUP_RST_N_REG BIT0 > + > +#define RESET_CONTROL_2 0x010 > + > +#define RESET_SELECT_1 0x014 > +#define SQU_RST_SEL BIT29 > +#define PHY_RST_SEL BIT28 > +#define PWR_RST_SEL BIT24 > +#define STI_RST_SEL BIT20 > +#define N_STI_RST_SEL BIT16 > +#define CORE_RST_SEL BIT12 > +#define PERST_SEL BIT4 > +#define BUTTON_RST_SEL BIT1 > +#define PWUP_RST_SEL BIT0 > + > +#define RESET_SELECT_2 0x018 > +#define DBI_ARST_SEL BIT8 > +#define SLV_ARST_SEL BIT4 > +#define MSTR_ARST_SEL BIT0 > + > +#define EM_CONTROL 0x030 > +#define PRE_DET_STT_REG BIT4 > + > +#define EM_SELECT 0x034 > +#define PRE_DET_STT_SEL BIT4 > + > +#define PM_CONTROL_2 0x050 > +#define SYS_AUX_PWR_DET BIT8 > + > +#define PHY_CONFIG_COM_6 0x114 > +#define PIPE_PORT_SEL (BIT1 | BIT0) > + > +#define LINK_MONITOR 0x210 > +#define SMLH_LINK_UP BIT0 > + > +#define LINK_CAPABILITIES_REG 0x07C > +#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4) > +#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0) > + > +#define LINK_CONTROL_LINK_STATUS_REG 0x080 > +#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20) > +#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16) > + > +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 > +#define BASE_CLASS_CODE 0xFF000000 > +#define BASE_CLASS_CODE_VALUE 0x06 > +#define SUBCLASS_CODE 0x00FF0000 > +#define SUBCLASS_CODE_VALUE 0x04 > +#define PROGRAM_INTERFACE 0x0000FF00 > +#define PROGRAM_INTERFACE_VALUE 0x00 > + > +#define MISC_CONTROL_1_OFF 0x8BC > +#define DBI_RO_WR_EN BIT0 > > STATIC > VOID > -- > 2.11.0 >