From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F3581221786B1 for ; Thu, 30 Nov 2017 10:49:37 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id z34so7644253wrz.10 for ; Thu, 30 Nov 2017 10:54:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=wXx9CsBqWsZKOACn2JavAvZp1zq0VtrL+MUwizCuWLU=; b=Iyo8EL5fPGIjOD0YaLAbHd5SE6PiEE8USJVc1d+u+5Bo4UYH86BDdn2XoL2h//atRC Mswg35i0hHrzo96ri0jrR1Q0fk46fPr0feC7Xe51jDrNR3SgcITStCcsNDlvLho8Hdwk Q66CrOAhQjIdTLur9kAM4mnKNBSgpJrLgyszQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=wXx9CsBqWsZKOACn2JavAvZp1zq0VtrL+MUwizCuWLU=; b=ZpZmvh3T4LYfC3ECOoe9S6Bwt5D1lCqEjQgOR4iVCrrKHsmtDJVBhdJ5lOyjVOmOpG ymVf5ORm5J5BArMgjW6uvSOqEs4mxheWsflKFjpm+r2pR56QZDqHUke28KwrPj4Wgits +wO66WPw56IdMAIQi8tISXMX4W7XgcX6c7Uzxq3B4CigLOJ7W8xMBKMQj9Qgf0xY9hDb hBT7O4UIdh06gPQihmxqdMI2QvKy7TMTqw6//WyTXALHWoh1WGrZkRHR0O5f9bqnknb7 YRQh5b57/J63PXYsF33kJXp/1Ysb9MM1GskqXESiOwVV9wT3sQEBFCR7EN8o1OUiuv1i KevQ== X-Gm-Message-State: AJaThX7zOw9XUCXqyAcnrvs7ADJxVfEu29Wci3PRsR4RfWVwdV6d6Ga0 tvZjyog50f6VErHbrU8/SlG9x2kr27A= X-Google-Smtp-Source: AGs4zMbgfDWlvLXykBQK6liuOJY3JWMJquxcaAki4QASXd3M7vAfkdDaL/ucXeHG7LYpqocUouD/+Q== X-Received: by 10.223.199.212 with SMTP id y20mr3176830wrg.60.1512068040824; Thu, 30 Nov 2017 10:54:00 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id p81sm2422326wrc.61.2017.11.30.10.53.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Nov 2017 10:53:59 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Thu, 30 Nov 2017 18:53:55 +0000 Message-Id: <20171130185355.20985-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH edk2-platforms v2] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Nov 2017 18:49:38 -0000 As it turns out, it is surprisingly easy to configure both the NETSEC and eMMC devices as cache coherent for DMA, given that they are both behind the same SMMU which is already configured in passthrough mode by the firmware running on the SCP. So update the static SMMU configuration to make memory accesses performed by these devices inner shareable inner/outer writeback cacheable, which makes them cache coherent with the CPUs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v2: update DeveloperBox as well update commit log to clarify that the SMMU is configured in pass through mode by the firmware running on the Cortex-M3 SCP Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 +- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ 7 files changed, 35 insertions(+), 3 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 7ca9fb104311..e1183b529b73 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -600,7 +600,7 @@ [Components.common] NetworkPkg/HttpBootDxe/HttpBootDxe.inf Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf } # diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 10da45ad2837..637f6d414d24 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -592,7 +592,7 @@ [Components.common] NetworkPkg/HttpBootDxe/HttpBootDxe.inf Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf } # diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 5e663c59efbd..ec784c70afe7 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -456,6 +456,7 @@ max-speed = <1000>; max-frame-size = <9000>; phy-handle = <ðphy0>; + dma-coherent; #address-cells = <1>; #size-cells = <0>; @@ -557,6 +558,7 @@ fujitsu,cmd-dat-delay-select; clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; + dma-coherent; status = "disabled"; }; }; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c index e577076ada4f..5a99283977fb 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -191,7 +191,7 @@ RegisterEmmc ( Status = RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, - NonDiscoverableDeviceDmaTypeNonCoherent, + NonDiscoverableDeviceDmaTypeCoherent, NULL, &mSdMmcControllerHandle, 1, diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index c64ccf3b3c30..7e7c790a6113 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -123,6 +123,27 @@ FreeDevice: return Status; } +#define SMMU_SCR0 0x0 +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22) +#define SMMU_SCR0_MTCFG (0x1 << 20) +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16) + +STATIC +VOID +SmmuEnableCoherentDma ( + VOID + ) +{ + // + // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and + // is configured in passthrough mode by default. Let's set the global memory + // type override as well, so that all memory accesses by these devices are + // inner shareable inner/outer writeback cacheable. + // + MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0, + SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB); +} + EFI_STATUS EFIAPI PlatformDxeEntryPoint ( @@ -174,5 +195,7 @@ PlatformDxeEntryPoint ( Status = RegisterEmmc (); ASSERT_EFI_ERROR (Status); + SmmuEnableCoherentDma (); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index 3c7bd58866cc..f43adcc8607f 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -65,4 +65,8 @@ #define SYNQUACER_PCIE_BASE 0x58200000 #define SYNQUACER_PCIE_SIZE 0x00200000 +// SCB SMMU +#define SYNQUACER_SCB_SMMU_BASE 0x52E00000 +#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB + #endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index a640b3e0c0d1..1402ecafce4a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)), ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase), FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)), + + // NETSEC/eMMC SMMU + ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE), }; STATIC -- 2.11.0