From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D42D21A10968 for ; Fri, 1 Dec 2017 05:04:47 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id 64so3270487wme.3 for ; Fri, 01 Dec 2017 05:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=7PtaIuu6k81S+LQNaAoxdjvQSorgpyBkvJ6sXf+gV4Y=; b=aQUOoheCJBLeeG0kGeZlQewT/DNJ3lM3iB+eLxrg5MBXr1QDfRIa32LyGLB/Fs7TaM haYbgk/K/QBV+aG6cEBIuZ9Sv/hY4qAsar/vzC1KQweC51LVP0XRE+SDv14qUATf6kRl Ydy1g3EUj6vKGDEugOftOglL/Y44Avzx7vOPU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=7PtaIuu6k81S+LQNaAoxdjvQSorgpyBkvJ6sXf+gV4Y=; b=KzMgDmnJOIkA/9qCm6HG22i3EsmpO51KvpthoWOuHmX0+0c1rtZGAylcTFMzrPAfdz 6LZzv1Wdj3L4D3EOuH1TFkVhfJk/qPD3+F7OCYAawaT12y7xT4QqJVH2KSAOs6IV5Xxt PwnHLgbzdQJZRIUajDG7BMTbtZRMfzJ6W8wR1k3QTjfYO8KEEv/tYo66gjXLSSfqhmQE tRasYh5sI+pTgbNylaEHHFBV6SeAy+SBT2eUVh188isvemb08woUSmd7o8ozClLHlirY cAG1DX1BZRPNrCl8IuUgI1ikax6qWn+jLxAb4JnbxELQzJ2BOoILdoTDKGGBENptIFCy J+zQ== X-Gm-Message-State: AKGB3mJPkZYRQ8E3l0DJhb2zLTgd2tvr223uzkgYMayei+HT4pW9DbHE w2MvtMU/rkObXGJptJl5kmjBvw== X-Google-Smtp-Source: AGs4zMZ6+ss1JG+vYfr1mZsSCY9vpcktD36mbrYh6YajGCjT7uGJXwGAE9puBLuI9UhbOJEJSnXOtA== X-Received: by 10.28.95.7 with SMTP id t7mr1135548wmb.86.1512133752133; Fri, 01 Dec 2017 05:09:12 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id w133sm1053112wmg.9.2017.12.01.05.09.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Dec 2017 05:09:10 -0800 (PST) Date: Fri, 1 Dec 2017 13:09:09 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171201130909.yfc5ddlk6ne2wov6@bivouac.eciton.net> References: <1512095334-20345-1-git-send-email-mw@semihalf.com> <1512095334-20345-5-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1512095334-20345-5-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 4/4] Marvell/Drivers: MvPhyDxe: Cleanup the header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Dec 2017 13:04:47 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Dec 01, 2017 at 03:28:54AM +0100, Marcin Wojtas wrote: > This patch removes unused macros defined in MvPhyDxe.h, as well > as improves the style and comments. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 2 +- > Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 152 ++++---------------- > 2 files changed, 31 insertions(+), 123 deletions(-) > > diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c > index e776a91..203dce2 100644 > --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c > +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c > @@ -201,7 +201,7 @@ MvPhyParseStatus ( > > DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link")); > while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { > - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { > + if (i > PHY_ANEG_TIMEOUT) { I'm down with the cleanup, but this change is not needed, and ANEG most certainly isn't an approved abbreviation. Please leave it as is. > DEBUG((DEBUG_ERROR," TIMEOUT !\n")); > PhyDev->LinkUp = FALSE; > break; > diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h > index 0c3d935..3cfcb80 100644 > --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h > +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h > @@ -34,137 +34,45 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #ifndef __MV_PHY_DXE_H__ > #define __MV_PHY_DXE_H__ > > -#define MII_BMCR 0x00 /* Basic mode control Register */ > -#define MII_BMSR 0x01 /* Basic mode status Register */ > -#define MII_PHYSID1 0x02 /* PHYS ID 1 */ > -#define MII_PHYSID2 0x03 /* PHYS ID 2 */ > -#define MII_ADVERTISE 0x04 /* Advertisement control Reg */ > -#define MII_LPA 0x05 /* Link partner ability Reg */ > -#define MII_EXPANSION 0x06 /* Expansion Register */ > -#define MII_CTRL1000 0x09 /* 1000BASE-T control */ > -#define MII_STAT1000 0x0a /* 1000BASE-T status */ > -#define MII_ESTATUS 0x0f /* Extended Status */ > -#define MII_DCOUNTER 0x12 /* Disconnect counter */ > -#define MII_FCSCOUNTER 0x13 /* False carrier counter */ > -#define MII_NWAYTEST 0x14 /* N-way auto-neg test Reg */ > -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ > -#define MII_SREVISION 0x16 /* Silicon revision */ > -#define MII_RESV1 0x17 /* Reserved... */ > -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ > -#define MII_PHYADDR 0x19 /* PHY address */ > -#define MII_RESV2 0x1a /* Reserved... */ > -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ > -#define MII_NCONFIG 0x1c /* Network interface config */ > - > -/* Basic mode control Register. */ > -#define BMCR_RESV 0x003f /* Unused... */ > -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ > -#define BMCR_CTST 0x0080 /* Collision test */ > -#define BMCR_FULLDPLX 0x0100 /* Full duplex */ > -#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ > -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ > -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ > -#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ > -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ > -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ > -#define BMCR_RESET 0x8000 /* Reset the DP83840 */ > - > -/* Basic mode status Register. */ > -#define BMSR_ERCAP 0x0001 /* Ext-Reg capability */ > -#define BMSR_JCD 0x0002 /* Jabber detected */ > -#define BMSR_LSTATUS 0x0004 /* Link status */ > -#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ > -#define BMSR_RFAULT 0x0010 /* Remote fault detected */ > -#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ > -#define BMSR_RESV 0x00c0 /* Unused... */ > -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ > -#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ > -#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ > -#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ > -#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ > -#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ > -#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ > -#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ > - > -#define PHY_ANEG_TIMEOUT 4000 > - > -#define PHY_INTERFACE_MODE_RGMII 0 > -#define PHY_INTERFACE_MODE_RGMII_ID 1 > -#define PHY_INTERFACE_MODE_RGMII_RXID 2 > -#define PHY_INTERFACE_MODE_RGMII_TXID 3 > -#define PHY_INTERFACE_MODE_SGMII 4 > -#define PHY_INTERFACE_MODE_RTBI 5 > - > -#define PHY_AUTONEGOTIATE_TIMEOUT 5000 Leave this. > +#define MII_BMCR 0x00 /* Basic mode control Register */ > +#define MII_BMSR 0x01 /* Basic mode status Register */ > + > +/* BMCR */ > +#define BMCR_ANRESTART 0x0200 /* 1 = Restart autonegotiation */ > +#define BMCR_ISOLATE 0x0400 /* 0 = Isolate PHY */ > +#define BMCR_ANENABLE 0x1000 /* 1 = Enable autonegotiation */ > +#define BMCR_RESET 0x8000 /* 1 = Reset the PHY */ > + > +/* BSMR */ > +#define BMSR_LSTATUS 0x0004 /* 1 = Link up */ > +#define BMSR_ANEGCAPABLE 0x0008 /* 1 = Able to perform auto-neg */ > +#define BMSR_ANEGCOMPLETE 0x0020 /* 1 = Auto-neg complete */ > + > +#define PHY_ANEG_TIMEOUT 5000 Drop this. / Leif > > /* 88E1011 PHY Status Register */ > -#define MIIM_88E1xxx_PHY_STATUS 0x11 > -#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 > -#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 > -#define MIIM_88E1xxx_PHYSTAT_100 0x4000 > -#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 > -#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 > -#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 > - > -#define MIIM_88E1xxx_PHY_SCR 0x10 > -#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 > - > -/* 88E1111 PHY LED Control Register */ > -#define MIIM_88E1111_PHY_LED_CONTROL 24 > -#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 > -#define MIIM_88E1111_PHY_LED_COMBINE 0x411C > +#define MIIM_88E1xxx_PHY_STATUS 0x11 > +#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 > +#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 > +#define MIIM_88E1xxx_PHYSTAT_100 0x4000 > +#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 > +#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 > +#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 > > /* 88E1111 Extended PHY Specific Control Register */ > -#define MIIM_88E1111_PHY_EXT_CR 0x14 > -#define MIIM_88E1111_RX_DELAY 0x80 > -#define MIIM_88E1111_TX_DELAY 0x2 > +#define MIIM_88E1111_PHY_EXT_CR 0x14 > +#define MIIM_88E1111_RX_DELAY 0x80 > +#define MIIM_88E1111_TX_DELAY 0x02 > > /* 88E1111 Extended PHY Specific Status Register */ > -#define MIIM_88E1111_PHY_EXT_SR 0x1b > -#define MIIM_88E1111_HWCFG_MODE_MASK 0xf > +#define MIIM_88E1111_PHY_EXT_SR 0x1b > +#define MIIM_88E1111_HWCFG_MODE_MASK 0xf > #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb > -#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 > +#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 > #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 > -#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 > +#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 > #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 > -#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 > - > -#define MIIM_88E1111_COPPER 0 > -#define MIIM_88E1111_FIBER 1 > - > -/* 88E1118 PHY defines */ > -#define MIIM_88E1118_PHY_PAGE 22 > -#define MIIM_88E1118_PHY_LED_PAGE 3 > - > -/* 88E1121 PHY LED Control Register */ > -#define MIIM_88E1121_PHY_LED_CTRL 16 > -#define MIIM_88E1121_PHY_LED_PAGE 3 > -#define MIIM_88E1121_PHY_LED_DEF 0x0030 > - > -/* 88E1121 PHY IRQ Enable/Status Register */ > -#define MIIM_88E1121_PHY_IRQ_EN 18 > -#define MIIM_88E1121_PHY_IRQ_STATUS 19 > - > -#define MIIM_88E1121_PHY_PAGE 22 > - > -/* 88E1145 Extended PHY Specific Control Register */ > -#define MIIM_88E1145_PHY_EXT_CR 20 > -#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 > -#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 > - > -#define MIIM_88E1145_PHY_LED_CONTROL 24 > -#define MIIM_88E1145_PHY_LED_DIRECT 0x4100 > - > -#define MIIM_88E1145_PHY_PAGE 29 > -#define MIIM_88E1145_PHY_CAL_OV 30 > - > -#define MIIM_88E1149_PHY_PAGE 29 > - > -/* 88E1310 PHY defines */ > -#define MIIM_88E1310_PHY_LED_CTRL 16 > -#define MIIM_88E1310_PHY_IRQ_EN 18 > -#define MIIM_88E1310_PHY_RGMII_CTRL 21 > -#define MIIM_88E1310_PHY_PAGE 22 > +#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 > > typedef enum { > MV_PHY_DEVICE_1512 > -- > 2.7.4 >