[PATCH v2 0/4] Enable page table write protection

[PATCH v2 0/4] Enable page table write protection

[Jian J Wang]

> v2 changes:
>  a. Enable protection on any newly added page table after DxeIpl.
>  b. Introduce page table pool concept to make page table allocation
>     and protection easier and error free.

Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe.
But the memory pages used for page table are not set as read-only in the driver
DxeIplPeim, after the paging is setup. This might jeopardize the page table
integrity if there's buffer overflow occured in other part of system.

This patch series will change this situation by clearing R/W bit in page attribute
of the pages used as page table.

Validation works include booting Windows (10/server 2016) and Linux (Fedora/Ubuntu)
on OVMF and Intel real platform.

Jian J Wang (4):
  MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
  MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
  MdeModulePkg/DxeIpl: Mark page table as read-only
  UefiCpuPkg/CpuDxe: Enable protection for newly added page table

 MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
 MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315 +++++++++++++++++++++-
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
 MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
 MdeModulePkg/MdeModulePkg.dec                    |  28 ++
 UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
 UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
 UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
 UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329 ++++++++++++++++++++++-
 UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
 12 files changed, 816 insertions(+), 13 deletions(-)
 create mode 100644 MdeModulePkg/Include/Guid/PageTablePool.h

-- 
2.14.1.windows.1

[PATCH v2 1/4] MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid

[Jian J Wang]

> v2:
>   newly added

PcdPageTablePoolUnitSize is used to specify the smallest size of memory pool
reserved for page table.

PcdPageTablePoolAlignment is used to specify the alignment of the memory pool
reserved for page table.

gPageTablePoolGuid is used to identify the memory pool used for page table.

These definitions are used to simplify the page table creation and protection.
They are also used to make sure that DxeIpl and CpuDxe driver are using the
same way to allocate page table memory.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
 MdeModulePkg/MdeModulePkg.dec | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 856d67aceb..075d51f807 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -392,6 +392,9 @@
   ## Include/Guid/PlatformHasAcpi.h
   gEdkiiPlatformHasAcpiGuid = { 0xf0966b41, 0xc23f, 0x41b9, { 0x96, 0x04, 0x0f, 0xf7, 0xe1, 0x11, 0x96, 0x5a } }
 
+  ## Include/Guid/PageTablePool.h
+  gPageTablePoolGuid = { 0x18347A49, 0xF48B, 0x4012, {0x67, 0x1D, 0x70, 0x23, 0x76, 0x5C, 0x92, 0xAD} }
+
 [Ppis]
   ## Include/Ppi/AtaController.h
   gPeiAtaControllerPpiGuid       = { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }}
@@ -949,6 +952,31 @@
   # @Prompt The Heap Guard feature mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0|UINT8|0x30001054
 
+  ## Specifiy the size in byte of memory unit allocated for page table.
+  #
+  #  This PCD is used for reserving certain amount of pages for page table
+  #  initialization. If pages reserved at last time are used up, another amount
+  #  of memory specified by this PCD will be allocated again, until all page
+  #  tables are initialized.
+  #
+  #  It's designed to reduce the recursive "split" action from larger
+  #  granularity to smaller one, and simplify the page table protection. Its
+  #  value must be the same as one of page sizes supported by the processor and
+  #  should be larger than the size of one page table.
+  #
+  # @Prompt Size of memory unit allocated for page table.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolUnitSize|0x200000|UINT32|0x30001060
+
+  ## Specifiy the alignment of page table pool.
+  #
+  #  This PCD is used for reserving page table pool at desired alignment boundary.
+  #  It's designed to reduce the recursive "split" action from larger granularity
+  #  to smaller one, and simplify the page table protection. Its value should
+  #  not be less than PcdPageTablePoolUnitSize for IA32 processor.
+  #
+  # @Prompt Alignment of page pool memory unit.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolAlignment|0x200000|UINT32|0x30001061
+
 [PcdsFixedAtBuild, PcdsPatchableInModule]
   ## Dynamic type PCD can be registered callback function for Pcd setting action.
   #  PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of callback function
-- 
2.14.1.windows.1

[PATCH v2 2/4] MdeModulePkg/PageTablePool.h: Page table pool GUID definition file

[Jian J Wang]

> v2:
>    newly added

This file is added to definition of gPageTablePoolGuid. In addition,
following structure type is defined to describe the page table pool
information which can be used by different drivers to allocate memory
for new page tables. It's supposed to be at the start address of each
separated pool. The NextPool field is used to link all the pools
together which helps to track and manage all the page tables easily.

typedef struct {
  EFI_GUID              Signature;
  EFI_PHYSICAL_ADDRESS  NextPool;
  UINT64                Offset;
  UINT64                FreePages;
} PAGE_TABLE_POOL_HEADER;

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
 MdeModulePkg/Include/Guid/PageTablePool.h | 53 +++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 MdeModulePkg/Include/Guid/PageTablePool.h

diff --git a/MdeModulePkg/Include/Guid/PageTablePool.h b/MdeModulePkg/Include/Guid/PageTablePool.h
new file mode 100644
index 0000000000..103739a9db
--- /dev/null
+++ b/MdeModulePkg/Include/Guid/PageTablePool.h
@@ -0,0 +1,53 @@
+/** @file
+  GUID used to identify the memory pool used for page table.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PAGE_TABLE_POOL_H__
+#define __PAGE_TABLE_POOL_H__
+
+///
+/// GUID value used to identify page table pool.
+///
+/// [18347A49-F48B-4012-671D-7023765C92AD]
+///
+#define PAGE_TABLE_POOL_GUID \
+  { \
+    0x18347A49, 0xF48B, 0x4012, {0x67, 0x1D, 0x70, 0x23, 0x76, 0x5C, 0x92, 0xAD} \
+  }
+
+///
+/// A structure at the header of first page in each page table pool.
+///
+typedef struct {
+  ///
+  /// Signature used to identify the memory pool used for page table.
+  ///
+  EFI_GUID              Signature;
+  ///
+  /// The address pointing to the header of next page table pool.
+  ///
+  EFI_PHYSICAL_ADDRESS  NextPool;
+  ///
+  /// The offset (in bytes) of free pages in current pool.
+  ///
+  UINT64                Offset;
+  ///
+  /// The number of free pages.
+  ///
+  UINT64                FreePages;
+} PAGE_TABLE_POOL_HEADER;
+
+extern EFI_GUID gPageTablePoolGuid;
+
+#endif  //__PAGE_TABLE_POOL_H__
-- 
2.14.1.windows.1

[PATCH v2 3/4] MdeModulePkg/DxeIpl: Mark page table as read-only

[Jian J Wang]

> v2:
>    Introduce page table pool to ease the page table memory allocation and
>    protection, which replaces the direct calling of AllocatePages().

This patch will set the memory pages used for page table as read-only
memory after the paging is setup. CR0.WP must set to let it take into
effect.

A simple page table memory management mechanism, page table pool concept,
is introduced to simplify the page table memory allocation and protection.
It will also help to reduce the potential recursive "split" action during
updating memory paging attributes.

The basic idea is to allocate a bunch of continuous pages of memory in
advance as one or more page table pools, and all future page tables
consumption will happen in those pool instead of system memory. If the page
pool is reserved at the boundary of 2MB page and with same size of 2MB page,
there's no page granularity "split" operation will be needed, because the
memory of new page tables (if needed) will be usually in the same page as
target page table you're working on.

And since we have centralized page tables (a few 2MB pages), it's easier
to protect them by changing their attributes to be read-only once and for
all. There's no need to apply the protection for new page tables any more
as long as the pool has free pages available.

Once current page table pool has been used up, one can allocate another 2MB
memory pool and just set this new 2MB memory block to be read-only instead of
setting the new page tables one page by one page.

Two new PCDs PcdPageTablePoolUnitSize and PcdPageTablePoolAlignment are used
to specify the size and alignment for page table pool. For IA32 processor
0x200000 (2MB) is the only choice for both of them to meet the requirement of
page table pool.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
 MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
 MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315 ++++++++++++++++++++++-
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
 5 files changed, 371 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h
index f3aabdb7e0..9dc80b1508 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h
@@ -265,4 +265,38 @@ IsNullDetectionEnabled (
   VOID
   );
 
+/**
+  Prevent the memory pages used for page table from been overwritten.
+
+  @param[in] PageTableBase    Base address of page table (CR3).
+
+**/
+VOID
+EnablePageTableProtection (
+  IN  UINTN     PageTableBase,
+  IN  BOOLEAN   Level4Paging
+  );
+
+/**
+  This API provides a way to allocate memory for page table.
+
+  This API can be called more than once to allocate memory for page tables.
+
+  Allocates the number of 4KB pages and returns a pointer to the allocated
+  buffer. The buffer returned is aligned on a 4KB boundary.
+
+  If Pages is 0, then NULL is returned.
+  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+AllocatePageTableMemory (
+  IN UINTN           Pages
+  );
+
 #endif
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index a1b8748432..e9ab74a800 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -102,6 +102,7 @@
   ## SOMETIMES_CONSUMES ## Variable:L"MemoryTypeInformation"
   ## SOMETIMES_PRODUCES ## HOB
   gEfiMemoryTypeInformationGuid
+  gPageTablePoolGuid    ## CONSUMES
 
 [FeaturePcd.IA32]
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode      ## CONSUMES
@@ -117,6 +118,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask    ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolUnitSize               ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolAlignment              ## CONSUMES
 
 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack               ## SOMETIMES_CONSUMES
diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
index 5649265367..13fff28e93 100644
--- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
@@ -99,7 +99,7 @@ Create4GPageTablesIa32Pae (
   NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));
 
   TotalPagesNum = NumberOfPdpEntriesNeeded + 1;
-  PageAddress = (UINTN) AllocatePages (TotalPagesNum);
+  PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
   ASSERT (PageAddress != 0);
 
   PageMap = (VOID *) PageAddress;
@@ -149,6 +149,12 @@ Create4GPageTablesIa32Pae (
       );
   }
 
+  //
+  // Protect the page table by marking the memory used for page table to be
+  // read-only.
+  //
+  EnablePageTableProtection ((UINTN)PageMap, FALSE);
+
   return (UINTN) PageMap;
 }
 
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 29b6205e88..e22a105eb3 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -31,6 +31,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include "DxeIpl.h"
 #include "VirtualMemory.h"
 
+#define PAGE_TABLE_POOL_ALIGN_MASK   \
+    (~(EFI_PHYSICAL_ADDRESS)(FixedPcdGet32 (PcdPageTablePoolAlignment) - 1))
+
+//
+// Global variable to keep track current available memory used as page table.
+//
+PAGE_TABLE_POOL_HEADER   *mPageTablePool = NULL;
+
 /**
   Clear legacy memory located at the first 4K-page, if available.
 
@@ -117,6 +125,127 @@ EnableExecuteDisableBit (
   AsmWriteMsr64 (0xC0000080, MsrRegisters);
 }
 
+/**
+  Initialize a buffer pool for page table use only.
+
+  To reduce the potential split operation on page table, the pages reserved for
+  page table should be allocated in the times of 512 (= SIZE_2MB) and at the
+  boundary of SIZE_2MB. So the page pool is always initialized with number of
+  pages greater than or equal to the given PoolPages.
+
+  Once the pages in the pool are used up, this method should be called again to
+  reserve at least another 512 pages. But usually this won't happen in practice.
+
+  @param PoolPages  The least page number of the pool to be created.
+
+  @retval TRUE    The pool is initialized successfully.
+  @retval FALSE   The memory is out of resource.
+**/
+BOOLEAN
+InitializePageTablePool (
+  IN UINTN           PoolPages
+  )
+{
+  VOID          *Buffer;
+  UINTN         PoolUnitPages;
+
+  //
+  // Make sure that page table pool is effective and efficient.
+  //
+  ASSERT (PcdGet32 (PcdPageTablePoolUnitSize) > EFI_PAGE_SIZE);
+  ASSERT (PcdGet32 (PcdPageTablePoolAlignment) == PcdGet32 (PcdPageTablePoolUnitSize));
+
+  //
+  // Always reserve at least PcdPageTablePoolUnitSize.
+  //
+  PoolUnitPages = EFI_SIZE_TO_PAGES (PcdGet32 (PcdPageTablePoolUnitSize));
+  if (PoolPages <= PoolUnitPages) {
+    PoolPages = PoolUnitPages;
+  } else {
+    PoolPages = ((PoolPages + PoolUnitPages) % PoolUnitPages) * PoolUnitPages;
+  }
+
+  Buffer = AllocateAlignedPages (
+             PoolPages,
+             FixedPcdGet32 (PcdPageTablePoolAlignment)
+             );
+  if (Buffer == NULL) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Out of pages aligned at 0x%x\n",
+            FixedPcdGet32 (PcdPageTablePoolAlignment)));
+    return FALSE;
+  }
+
+  DEBUG ((DEBUG_INFO, "Allocated %d pages at %x!\r\n", PoolPages, Buffer));
+  if (mPageTablePool == NULL) {
+    mPageTablePool = Buffer;
+    mPageTablePool->NextPool = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+  }
+
+  //
+  // Link all pools into a list.
+  //
+  ((PAGE_TABLE_POOL_HEADER *)Buffer)->NextPool = mPageTablePool->NextPool;
+  mPageTablePool->NextPool = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+
+  //
+  // Reserve one page for pool header.
+  //
+  mPageTablePool = Buffer;
+  CopyMem (&mPageTablePool->Signature, &gPageTablePoolGuid, sizeof (EFI_GUID));
+  mPageTablePool->FreePages  = PoolPages - 1;
+  mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
+
+  return TRUE;
+}
+
+/**
+  This API provides a way to allocate memory for page table.
+
+  This API can be called more than once to allocate memory for page tables.
+
+  Allocates the number of 4KB pages and returns a pointer to the allocated
+  buffer. The buffer returned is aligned on a 4KB boundary.
+
+  If Pages is 0, then NULL is returned.
+  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+AllocatePageTableMemory (
+  IN UINTN           Pages
+  )
+{
+  VOID          *Buffer;
+
+  if (Pages == 0) {
+    return NULL;
+  }
+
+  //
+  // Renew the pool if necessary.
+  //
+  if (mPageTablePool == NULL ||
+      Pages > mPageTablePool->FreePages) {
+    if (!InitializePageTablePool (Pages)) {
+      return NULL;
+    }
+  }
+
+  Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;
+
+  mPageTablePool->Offset     += EFI_PAGES_TO_SIZE (Pages);
+  mPageTablePool->FreePages  -= Pages;
+
+  DEBUG ((DEBUG_INFO, "Allocate total %d pages for page table!\r\n", RShiftU64 (mPageTablePool->Offset, 12)));
+
+  return Buffer;
+}
+
 /**
   Split 2M page to 4K.
 
@@ -144,7 +273,7 @@ Split2MPageTo4K (
   //
   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
 
-  PageTableEntry = AllocatePages (1);
+  PageTableEntry = AllocatePageTableMemory (1);
   ASSERT (PageTableEntry != NULL);
 
   //
@@ -204,7 +333,7 @@ Split1GPageTo2M (
   //
   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
 
-  PageDirectoryEntry = AllocatePages (1);
+  PageDirectoryEntry = AllocatePageTableMemory (1);
   ASSERT (PageDirectoryEntry != NULL);
 
   //
@@ -234,6 +363,180 @@ Split1GPageTo2M (
   }
 }
 
+/**
+  Set one page of page table pool memory to be read-only.
+
+  @param[in] PageTableBase    Base address of page table (CR3).
+  @param[in] Address          Start address of a page to be set as read-only.
+  @param[in] Level4Paging     Level 4 paging flag.
+
+**/
+VOID
+SetPageTablePoolReadOnly (
+  IN  UINTN                             PageTableBase,
+  IN  EFI_PHYSICAL_ADDRESS              Address,
+  IN  BOOLEAN                           Level4Paging
+  )
+{
+  UINTN                 Index;
+  UINTN                 EntryIndex;
+  UINT64                AddressEncMask;
+  EFI_PHYSICAL_ADDRESS  PhysicalAddress;
+  UINT64                *PageTable;
+  UINT64                *NewPageTable;
+  UINT64                PageAttr;
+  UINT64                LevelSize[5];
+  UINT64                LevelMask[5];
+  UINTN                 LevelShift[5];
+  UINTN                 Level;
+  UINT64                PoolUnitSize;
+
+  ASSERT (PageTableBase != 0);
+
+  //
+  // Since the page table is always from page table pool, which is always
+  // located at the boundary of PcdPageTablePoolAlignment, we just need to
+  // set the whole pool unit to be read-only.
+  //
+  Address = Address & PAGE_TABLE_POOL_ALIGN_MASK;
+
+  LevelShift[1] = PAGING_L1_ADDRESS_SHIFT;
+  LevelShift[2] = PAGING_L2_ADDRESS_SHIFT;
+  LevelShift[3] = PAGING_L3_ADDRESS_SHIFT;
+  LevelShift[4] = PAGING_L4_ADDRESS_SHIFT;
+
+  LevelMask[1] = PAGING_4K_ADDRESS_MASK_64;
+  LevelMask[2] = PAGING_2M_ADDRESS_MASK_64;
+  LevelMask[3] = PAGING_1G_ADDRESS_MASK_64;
+  LevelMask[4] = PAGING_1G_ADDRESS_MASK_64;
+
+  LevelSize[1] = SIZE_4KB;
+  LevelSize[2] = SIZE_2MB;
+  LevelSize[3] = SIZE_1GB;
+  LevelSize[4] = SIZE_512GB;
+
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
+                   PAGING_1G_ADDRESS_MASK_64;
+  PageTable = (UINT64 *)(UINTN)PageTableBase;
+  PoolUnitSize = PcdGet32 (PcdPageTablePoolUnitSize);
+  for (Level = (Level4Paging) ? 4 : 3; Level > 0; --Level) {
+    Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));
+    Index &= PAGING_PAE_INDEX_MASK;
+
+    PageAttr = PageTable[Index];
+    if ((PageAttr & IA32_PG_PS) == 0) {
+      //
+      // Go to next level of table.
+      //
+      PageTable = (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask &
+                                    PAGING_4K_ADDRESS_MASK_64);
+      continue;
+    }
+
+    //
+    // Clear R/W bit if current page granularity is not bigger than pool unit
+    // size.
+    //
+    if (PoolUnitSize >= LevelSize[Level]) {
+      if ((PageAttr & IA32_PG_RW) != 0) {
+        while (PoolUnitSize > 0) {
+          //
+          // PcdPageTablePoolUnitSize and PcdPageTablePoolAlignment must be set
+          // with values within one page (2MB by default). Then we don't need
+          // to update attributes for pages crossing page directory . ASSERT
+          // below is for that purpose.
+          //
+          ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64));
+
+          PageTable[Index] &= ~(UINT64)IA32_PG_RW;
+          PoolUnitSize -= LevelSize[Level];
+          ++Index;
+        }
+      }
+      break;
+    }
+
+    //
+    // The smaller granularity of page must be needed.
+    //
+    NewPageTable = AllocatePageTableMemory (1);
+    ASSERT (NewPageTable != NULL);
+
+    PhysicalAddress = PageAttr & LevelMask[Level];
+    for (EntryIndex = 0;
+          EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);
+          ++EntryIndex) {
+      NewPageTable[EntryIndex] = PhysicalAddress  | AddressEncMask |
+                                 IA32_PG_P | IA32_PG_RW;
+      if (Level > 1) {
+        NewPageTable[EntryIndex] |= IA32_PG_PS;
+      }
+      PhysicalAddress += LevelSize[Level];
+    }
+
+    PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |
+                                      IA32_PG_P | IA32_PG_RW;
+    PageTable = NewPageTable;
+  }
+}
+
+/**
+  Prevent the memory pages used for page table from been overwritten.
+
+  @param[in] PageTableBase    Base address of page table (CR3).
+
+**/
+VOID
+EnablePageTableProtection (
+  IN  UINTN     PageTableBase,
+  IN  BOOLEAN   Level4Paging
+  )
+{
+  PAGE_TABLE_POOL_HEADER  *HeadPool;
+  PAGE_TABLE_POOL_HEADER  *Pool;
+  UINT64                  PoolSize;
+  EFI_PHYSICAL_ADDRESS    Address;
+
+  if (mPageTablePool == NULL) {
+    return;
+  }
+
+  //
+  // Disable write protection, because we need to mark page table to be write
+  // protected.
+  //
+  AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
+
+  //
+  // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
+  // remember original one in advance.
+  //
+  HeadPool = mPageTablePool;
+  Pool = HeadPool;
+  do {
+    Address  = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool;
+    PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE ((UINTN)Pool->FreePages);
+
+    //
+    // The size of one pool must be multiple of PcdPageTablePoolUnitSize, which
+    // is one of page size of the processor (2MB by default). Let's apply the
+    // protection to them one by one.
+    //
+    while (PoolSize > 0) {
+      SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);
+      Address   += PcdGet32 (PcdPageTablePoolUnitSize);
+      PoolSize  -= PcdGet32 (PcdPageTablePoolUnitSize);
+    }
+
+    Pool = (PAGE_TABLE_POOL_HEADER *)(UINTN)Pool->NextPool;
+  } while (Pool != HeadPool);
+
+  //
+  // Enable write protection, after page table updated.
+  //
+  AsmWriteCr0 (AsmReadCr0() | CR0_WP);
+}
+
 /**
   Allocates and fills in the Page Directory and Page Table Entries to
   establish a 1:1 Virtual to Physical mapping.
@@ -329,7 +632,7 @@ CreateIdentityMappingPageTables (
   } else {
     TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
   }
-  BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);
+  BigPageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
   ASSERT (BigPageAddress != 0);
 
   //
@@ -430,6 +733,12 @@ CreateIdentityMappingPageTables (
       );
   }
 
+  //
+  // Protect the page table by marking the memory used for page table to be
+  // read-only.
+  //
+  EnablePageTableProtection ((UINTN)PageMap, TRUE);
+
   if (PcdGetBool (PcdSetNxForStack)) {
     EnableExecuteDisableBit ();
   }
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
index 7c9bb49e3e..73ec074c5d 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
@@ -22,6 +22,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #ifndef _VIRTUAL_MEMORY_H_
 #define _VIRTUAL_MEMORY_H_
 
+#include <Guid/PageTablePool.h>
 
 #define SYS_CODE64_SEL 0x38
 
@@ -148,11 +149,25 @@ typedef union {
 
 #pragma pack()
 
+#define CR0_WP                      BIT16
+
 #define IA32_PG_P                   BIT0
 #define IA32_PG_RW                  BIT1
+#define IA32_PG_PS                  BIT7
+
+#define PAGING_PAE_INDEX_MASK       0x1FF
 
+#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull
+#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull
 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull
 
+#define PAGING_L1_ADDRESS_SHIFT     12
+#define PAGING_L2_ADDRESS_SHIFT     21
+#define PAGING_L3_ADDRESS_SHIFT     30
+#define PAGING_L4_ADDRESS_SHIFT     39
+
+#define PAGING_PML4E_NUMBER         4
+
 /**
   Enable Execute Disable Bit.
 
-- 
2.14.1.windows.1

[PATCH v2 4/4] UefiCpuPkg/CpuDxe: Enable protection for newly added page table

[Jian J Wang]

> v2:
>    Use the page table pool to allocate new page tables and save code
>    to enable protection for them separately.

One of the functionalities of CpuDxe is to update memory paging attributes.
If page table protection is applied, it must be disabled temporarily before
any attributes update and enabled again afterwards.

Another job in this patch is to re-use the page table pool reserved in DxeIpl,
if there're still free pages in it. Otherwise, the driver will reserve another
block of memory (specified by PcdPageTablePoolUnitSize and
PcdPageTablePoolAlignment) as new page table pool. The protection will be only
applied to the whole pool instead of individual table pages. Same as DxeIpl,
this helps to reduce potential "split" operation and recursive calling of
SetMemorySpaceAttributes().

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
 UefiCpuPkg/CpuDxe/CpuDxe.c       |  17 +-
 UefiCpuPkg/CpuDxe/CpuDxe.h       |   2 +
 UefiCpuPkg/CpuDxe/CpuDxe.inf     |   3 +
 UefiCpuPkg/CpuDxe/CpuPageTable.c | 329 ++++++++++++++++++++++++++++++++++++++-
 UefiCpuPkg/CpuDxe/CpuPageTable.h |  22 +++
 5 files changed, 364 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 8ddebabd02..6ae2dcd1c7 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -25,6 +25,7 @@
 BOOLEAN                   InterruptState = FALSE;
 EFI_HANDLE                mCpuHandle = NULL;
 BOOLEAN                   mIsFlushingGCD;
+BOOLEAN                   mIsAllocatingPageTable = FALSE;
 UINT64                    mValidMtrrAddressMask;
 UINT64                    mValidMtrrBitsMask;
 UINT64                    mTimerPeriod = 0;
@@ -407,6 +408,20 @@ CpuSetMemoryAttributes (
     return EFI_SUCCESS;
   }
 
+  //
+  // During memory attributes updating, new pages may be allocated to setup
+  // smaller granularity of page table. Page allocation action might then cause
+  // another calling of CpuSetMemoryAttributes() recursively, due to memory
+  // protection policy configured (such as PcdDxeNxMemoryProtectionPolicy).
+  // Since this driver will always protect memory used as page table by itself,
+  // there's no need to apply protection policy requested from memory service.
+  // So it's safe to just return EFI_SUCCESS if this time of calling is caused
+  // by page table memory allocation.
+  //
+  if (mIsAllocatingPageTable) {
+    DEBUG((DEBUG_VERBOSE, "  Allocating page table memory\n"));
+    return EFI_SUCCESS;
+  }
 
   CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;
   MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;
@@ -487,7 +502,7 @@ CpuSetMemoryAttributes (
   //
   // Set memory attribute by page table
   //
-  return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);
+  return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL);
 }
 
 /**
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h
index 9c0d22359d..540f5f2dbf 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.h
@@ -273,5 +273,7 @@ RefreshGcdMemoryAttributesFromPaging (
   VOID
   );
 
+extern BOOLEAN mIsAllocatingPageTable;
+
 #endif
 
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 3e8d196739..0a45285427 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -74,6 +74,7 @@
 [Guids]
   gIdleLoopEventGuid                            ## CONSUMES           ## Event
   gEfiVectorHandoffTableGuid                    ## SOMETIMES_CONSUMES ## SystemTable
+  gPageTablePoolGuid                            ## CONSUMES
 
 [Ppis]
   gEfiSecPlatformInformation2PpiGuid            ## UNDEFINED # HOB
@@ -81,6 +82,8 @@
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolUnitSize               ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPageTablePoolAlignment              ## CONSUMES
 
 [Depex]
   TRUE
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index 9658ed74c5..03b54a2111 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -62,6 +62,9 @@
 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
 
+#define PAGE_TABLE_POOL_ALIGN_MASK   \
+    (~(EFI_PHYSICAL_ADDRESS)(FixedPcdGet32 (PcdPageTablePoolAlignment) - 1))
+
 typedef enum {
   PageNone,
   Page4K,
@@ -87,6 +90,8 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
   {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
 };
 
+PAGE_TABLE_POOL_HEADER   *mPageTablePool = NULL;
+
 /**
   Enable write protection function for AP.
 
@@ -172,10 +177,6 @@ GetCurrentPagingContext (
   }
   if ((AsmReadCr0 () & BIT31) != 0) {
     PagingContext->ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
-    if ((AsmReadCr0 () & BIT16) == 0) {
-      AsmWriteCr0 (AsmReadCr0 () | BIT16);
-      SyncMemoryPageAttributesAp (SyncCpuEnableWriteProtection);
-    }
   } else {
     PagingContext->ContextData.X64.PageTableBase = 0;
   }
@@ -561,6 +562,59 @@ SplitPage (
   }
 }
 
+/**
+ Check the WP status in CR0 register. This bit is used to lock or unlock write
+ access to pages marked as read-only.
+
+  @retval TRUE    Write protection is enabled.
+  @retval FALSE   Write protection is disabled.
+**/
+BOOLEAN
+IsReadOnlyPageWriteProtected (
+  VOID
+  )
+{
+  return ((AsmReadCr0 () & BIT16) != 0);
+}
+
+/**
+  Disable write protection function for AP.
+
+  @param[in,out] Buffer  The pointer to private data buffer.
+**/
+VOID
+EFIAPI
+SyncCpuDisableWriteProtection (
+  IN OUT VOID *Buffer
+  )
+{
+  AsmWriteCr0 (AsmReadCr0() & ~BIT16);
+}
+
+/**
+ Disable Write Protect on pages marked as read-only.
+**/
+VOID
+DisableReadOnlyPageWriteProtect (
+  VOID
+  )
+{
+  AsmWriteCr0 (AsmReadCr0() & ~BIT16);
+  SyncMemoryPageAttributesAp (SyncCpuDisableWriteProtection);
+}
+
+/**
+ Enable Write Protect on pages marked as read-only.
+**/
+VOID
+EnableReadOnlyPageWriteProtect (
+  VOID
+  )
+{
+  AsmWriteCr0 (AsmReadCr0() | BIT16);
+  SyncMemoryPageAttributesAp (SyncCpuEnableWriteProtection);
+}
+
 /**
   This function modifies the page attributes for the memory region specified by BaseAddress and
   Length from their current attributes to the attributes specified by Attributes.
@@ -609,6 +663,7 @@ ConvertMemoryPageAttributes (
   PAGE_ATTRIBUTE                    SplitAttribute;
   RETURN_STATUS                     Status;
   BOOLEAN                           IsEntryModified;
+  BOOLEAN                           IsWpEnabled;
 
   if ((BaseAddress & (SIZE_4KB - 1)) != 0) {
     DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));
@@ -665,14 +720,27 @@ ConvertMemoryPageAttributes (
   if (IsModified != NULL) {
     *IsModified = FALSE;
   }
+  if (AllocatePagesFunc == NULL) {
+    AllocatePagesFunc = AllocatePageTableMemory;
+  }
+
+  //
+  // Make sure that the page table is changeable.
+  //
+  IsWpEnabled = IsReadOnlyPageWriteProtected ();
+  if (IsWpEnabled) {
+    DisableReadOnlyPageWriteProtect ();
+  }
 
   //
   // Below logic is to check 2M/4K page to make sure we donot waist memory.
   //
+  Status = EFI_SUCCESS;
   while (Length != 0) {
     PageEntry = GetPageTableEntry (&CurrentPagingContext, BaseAddress, &PageAttribute);
     if (PageEntry == NULL) {
-      return RETURN_UNSUPPORTED;
+      Status = RETURN_UNSUPPORTED;
+      goto Done;
     }
     PageEntryLength = PageAttributeToLength (PageAttribute);
     SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
@@ -690,11 +758,13 @@ ConvertMemoryPageAttributes (
       Length -= PageEntryLength;
     } else {
       if (AllocatePagesFunc == NULL) {
-        return RETURN_UNSUPPORTED;
+        Status = RETURN_UNSUPPORTED;
+        goto Done;
       }
       Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);
       if (RETURN_ERROR (Status)) {
-        return RETURN_UNSUPPORTED;
+        Status = RETURN_UNSUPPORTED;
+        goto Done;
       }
       if (IsSplitted != NULL) {
         *IsSplitted = TRUE;
@@ -709,7 +779,14 @@ ConvertMemoryPageAttributes (
     }
   }
 
-  return RETURN_SUCCESS;
+Done:
+  //
+  // Restore page table write protection, if any.
+  //
+  if (IsWpEnabled) {
+    EnableReadOnlyPageWriteProtect ();
+  }
+  return Status;
 }
 
 /**
@@ -922,6 +999,230 @@ RefreshGcdMemoryAttributesFromPaging (
   FreePool (MemorySpaceMap);
 }
 
+/**
+  Try to find the page table pool reserved before.
+
+  Since the page table pool is always allocated at the boundary specified by
+  PcdPageTablePoolAlignment, we can definitely find the header address of pool
+  containing the page table given by CR3, by just checking the aligned address
+  lower than value of it.
+
+  @param[in] PagingContext  The paging context.
+
+  @retval Address of page table pool reserved before.
+  @retval NULL    The page table pool was not found.
+**/
+PAGE_TABLE_POOL_HEADER *
+FindPageTablePool (
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT   *PagingContext
+  )
+{
+  PAGE_TABLE_POOL_HEADER    *Pool;
+  VOID                      *BaseAddress;
+  UINTN                     Index;
+
+  BaseAddress = (VOID *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
+  for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (UINT64); ++Index) {
+    //
+    // Because the pool header occupies one page, let's always check the address
+    // one page before.
+    //
+    Pool = (VOID *)(UINTN)(((UINTN)BaseAddress - EFI_PAGE_SIZE) &
+                           PAGE_TABLE_POOL_ALIGN_MASK);
+
+    //
+    // Check the signature.
+    //
+    if (!CompareMem (&Pool->Signature, &gPageTablePoolGuid, sizeof (EFI_GUID))) {
+      return Pool;
+    }
+
+    //
+    // Check the address at previous alginment boundary.
+    //
+    BaseAddress = Pool;
+  }
+
+  return NULL;
+}
+
+/**
+  Initialize a buffer pool for page table use only.
+
+  To reduce the potential split operation on page table, the pages reserved for
+  page table should be allocated in the times of 512 (= SIZE_2MB) and at the
+  boundary of SIZE_2MB. So the page pool is always initialized with number of
+  pages greater than or equal to the given PoolPages.
+
+  Once the pages in the pool are used up, this method should be called again to
+  reserve at least another 512 pages. Usually this won't happen often in
+  practice.
+
+  But for the first time calling of this method, it will search page table pool
+  reserved before (DxeIpl) and try to re-use it if there're still free pages
+  in it.
+
+  @param[in] PagingContext  The paging context.
+  @param[in] PoolPages      The least page number of the pool to be created.
+
+  @retval TRUE    The pool is initialized successfully.
+  @retval FALSE   The memory is out of resource.
+**/
+BOOLEAN
+InitializePageTablePool (
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT   *PagingContext,
+  IN  UINTN                           PoolPages
+  )
+{
+  VOID                      *Buffer;
+  BOOLEAN                   IsModified;
+  PAGE_TABLE_POOL_HEADER    *HeadPool;
+  PAGE_TABLE_POOL_HEADER    *Pool;
+  UINTN                     PoolUnitPages;
+
+  //
+  // There must be page table pool already reserved in IPL or PEI. Let's reuse
+  // them if there're still pages available.
+  //
+  if (mPageTablePool == NULL) {
+    HeadPool = FindPageTablePool (PagingContext);
+
+    if (HeadPool != NULL) {
+      Pool = HeadPool;
+      do {
+        ASSERT (
+          !CompareMem (&Pool->Signature, &gPageTablePoolGuid, sizeof (EFI_GUID))
+          );
+
+        if (mPageTablePool == NULL ||
+            mPageTablePool->FreePages < Pool->FreePages) {
+          mPageTablePool = Pool;
+        }
+
+        Pool = (VOID *)(UINTN)Pool->NextPool;
+      } while (Pool != HeadPool);
+
+      //
+      // Enough pages available?
+      //
+      if (PoolPages <= mPageTablePool->FreePages) {
+        return TRUE;
+      }
+    }
+  }
+
+  //
+  // Reserve at least PcdPageTablePoolUnitSize.
+  //
+  PoolUnitPages = EFI_SIZE_TO_PAGES (PcdGet32 (PcdPageTablePoolUnitSize));
+  if (PoolPages <= PoolUnitPages) {
+    PoolPages = PoolUnitPages;
+  } else {
+    PoolPages = (PoolPages + PoolUnitPages) % PoolUnitPages;
+  }
+
+  //
+  // Set guard flag to avoid recursive calling of SetMemoryAttributes.
+  // Protection will be applied in this methond instead before return.
+  //
+  mIsAllocatingPageTable = TRUE;
+  Buffer = AllocateAlignedPages (
+             PoolPages,
+             FixedPcdGet32 (PcdPageTablePoolAlignment)
+             );
+  mIsAllocatingPageTable = FALSE;
+
+  if (Buffer == NULL) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Out of pages aligned at 0x%x\n",
+            FixedPcdGet32 (PcdPageTablePoolAlignment)));
+    return FALSE;
+  }
+
+  if (mPageTablePool == NULL) {
+    mPageTablePool = Buffer;
+    mPageTablePool->NextPool = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+  }
+
+  //
+  // Link all pools into a list.
+  //
+  ((PAGE_TABLE_POOL_HEADER *)Buffer)->NextPool = mPageTablePool->NextPool;
+  mPageTablePool->NextPool = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+
+  //
+  // Reserve one page for pool header.
+  //
+  mPageTablePool = Buffer;
+  CopyMem (&mPageTablePool->Signature, &gPageTablePoolGuid, sizeof (EFI_GUID));
+  mPageTablePool->FreePages  = PoolPages - 1;
+  mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
+
+  //
+  // Mark the whole pool pages as read-only.
+  //
+  ConvertMemoryPageAttributes (
+    NULL,
+    (PHYSICAL_ADDRESS)(UINTN)Buffer,
+    EFI_PAGES_TO_SIZE (PoolPages),
+    EFI_MEMORY_RO,
+    PageActionSet,
+    AllocatePageTableMemory,
+    NULL,
+    &IsModified
+    );
+  ASSERT (IsModified == TRUE);
+
+  return TRUE;
+}
+
+/**
+  This API provides a way to allocate memory for page table.
+
+  This API can be called more than once to allocate memory for page tables.
+
+  Allocates the number of 4KB pages and returns a pointer to the allocated
+  buffer. The buffer returned is aligned on a 4KB boundary.
+
+  If Pages is 0, then NULL is returned.
+  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocatePageTableMemory (
+  IN UINTN           Pages
+  )
+{
+  PAGE_TABLE_LIB_PAGING_CONTEXT   PagingContext;
+  VOID                            *Buffer;
+
+  if (Pages == 0) {
+    return NULL;
+  }
+
+  //
+  // Renew the pool if necessary.
+  //
+  if (Pages > mPageTablePool->FreePages) {
+    GetCurrentPagingContext (&PagingContext);
+    if (!InitializePageTablePool (&PagingContext, Pages)) {
+      return NULL;
+    }
+  }
+
+  Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;
+
+  mPageTablePool->Offset     += EFI_PAGES_TO_SIZE (Pages);
+  mPageTablePool->FreePages  -= Pages;
+
+  return Buffer;
+}
+
 /**
   Initialize the Page Table lib.
 **/
@@ -933,6 +1234,18 @@ InitializePageTableLib (
   PAGE_TABLE_LIB_PAGING_CONTEXT     CurrentPagingContext;
 
   GetCurrentPagingContext (&CurrentPagingContext);
+
+  //
+  // Reserve memory of page tables for future uses, if paging is enabled.
+  //
+  if (CurrentPagingContext.ContextData.X64.PageTableBase != 0 &&
+      (CurrentPagingContext.ContextData.Ia32.Attributes &
+       PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) {
+    DisableReadOnlyPageWriteProtect();
+    InitializePageTablePool (&CurrentPagingContext, 0);
+    EnableReadOnlyPageWriteProtect ();
+  }
+
   DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n", CurrentPagingContext.MachineType));
   DEBUG ((DEBUG_INFO, "  MachineType   - 0x%x\n", CurrentPagingContext.MachineType));
   DEBUG ((DEBUG_INFO, "  PageTableBase - 0x%x\n", CurrentPagingContext.ContextData.X64.PageTableBase));
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTable.h
index eaff595b4c..0faa11830d 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.h
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h
@@ -16,6 +16,7 @@
 #define _PAGE_TABLE_LIB_H_
 
 #include <IndustryStandard/PeImage.h>
+#include <Guid/PageTablePool.h>
 
 #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE              BIT0
 #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE              BIT1
@@ -110,4 +111,25 @@ InitializePageTableLib (
   VOID
   );
 
+/**
+  This API provides a way to allocate memory for page table.
+
+  This API can be called more once to allocate memory for page tables.
+
+  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocatePageTableMemory (
+  IN UINTN           Pages
+  );
+
 #endif
-- 
2.14.1.windows.1

Re: [PATCH v2 0/4] Enable page table write protection

[Zeng, Star]

Recommend to not introduce the new header file and PCDs as new interfaces, but handle the page table pool separately in DxeIpl and CpuDxe.

Thanks,
Star
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian J Wang
Sent: Monday, December 4, 2017 4:36 PM
To: edk2-devel@lists.01.org
Subject: [edk2] [PATCH v2 0/4] Enable page table write protection

> v2 changes:
>  a. Enable protection on any newly added page table after DxeIpl.
>  b. Introduce page table pool concept to make page table allocation
>     and protection easier and error free.

Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe.
But the memory pages used for page table are not set as read-only in the driver DxeIplPeim, after the paging is setup. This might jeopardize the page table integrity if there's buffer overflow occured in other part of system.

This patch series will change this situation by clearing R/W bit in page attribute of the pages used as page table.

Validation works include booting Windows (10/server 2016) and Linux (Fedora/Ubuntu) on OVMF and Intel real platform.

Jian J Wang (4):
  MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
  MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
  MdeModulePkg/DxeIpl: Mark page table as read-only
  UefiCpuPkg/CpuDxe: Enable protection for newly added page table

 MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
 MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315 +++++++++++++++++++++-  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
 MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
 MdeModulePkg/MdeModulePkg.dec                    |  28 ++
 UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
 UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
 UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
 UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329 ++++++++++++++++++++++-
 UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
 12 files changed, 816 insertions(+), 13 deletions(-)  create mode 100644 MdeModulePkg/Include/Guid/PageTablePool.h

--
2.14.1.windows.1

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Re: [PATCH v2 0/4] Enable page table write protection

[Wang, Jian J]

That means we can't share page table pool between DxeIpl and CpuDxe. If this is
acceptable, I can remove them.

> -----Original Message-----
> From: Zeng, Star
> Sent: Monday, December 04, 2017 5:11 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Dong,
> Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> Recommend to not introduce the new header file and PCDs as new interfaces,
> but handle the page table pool separately in DxeIpl and CpuDxe.
> 
> Thanks,
> Star
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian J
> Wang
> Sent: Monday, December 4, 2017 4:36 PM
> To: edk2-devel@lists.01.org
> Subject: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> > v2 changes:
> >  a. Enable protection on any newly added page table after DxeIpl.
> >  b. Introduce page table pool concept to make page table allocation
> >     and protection easier and error free.
> 
> Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe.
> But the memory pages used for page table are not set as read-only in the driver
> DxeIplPeim, after the paging is setup. This might jeopardize the page table
> integrity if there's buffer overflow occured in other part of system.
> 
> This patch series will change this situation by clearing R/W bit in page attribute
> of the pages used as page table.
> 
> Validation works include booting Windows (10/server 2016) and Linux
> (Fedora/Ubuntu) on OVMF and Intel real platform.
> 
> Jian J Wang (4):
>   MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
>   MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
>   MdeModulePkg/DxeIpl: Mark page table as read-only
>   UefiCpuPkg/CpuDxe: Enable protection for newly added page table
> 
>  MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
>  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
>  MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
>  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315
> +++++++++++++++++++++-
> MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
>  MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
>  MdeModulePkg/MdeModulePkg.dec                    |  28 ++
>  UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
>  UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
>  UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
>  UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329
> ++++++++++++++++++++++-
>  UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
>  12 files changed, 816 insertions(+), 13 deletions(-)  create mode 100644
> MdeModulePkg/Include/Guid/PageTablePool.h
> 
> --
> 2.14.1.windows.1
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel

Re: [PATCH v2 0/4] Enable page table write protection

[Yao, Jiewen]

I do not suggest we define PAGE_TABLE_POOL_HEADER.
If we can figure out other way, that will be better.

Thank you
Yao Jiewen


> -----Original Message-----
> From: Wang, Jian J
> Sent: Monday, December 4, 2017 5:26 PM
> To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Dong,
> Eric <eric.dong@intel.com>
> Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> That means we can't share page table pool between DxeIpl and CpuDxe. If this is
> acceptable, I can remove them.
> 
> > -----Original Message-----
> > From: Zeng, Star
> > Sent: Monday, December 04, 2017 5:11 PM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>;
> Dong,
> > Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> >
> > Recommend to not introduce the new header file and PCDs as new interfaces,
> > but handle the page table pool separately in DxeIpl and CpuDxe.
> >
> > Thanks,
> > Star
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Monday, December 4, 2017 4:36 PM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] [PATCH v2 0/4] Enable page table write protection
> >
> > > v2 changes:
> > >  a. Enable protection on any newly added page table after DxeIpl.
> > >  b. Introduce page table pool concept to make page table allocation
> > >     and protection easier and error free.
> >
> > Write Protect feature (CR0.WP) is always enabled in driver
> UefiCpuPkg/CpuDxe.
> > But the memory pages used for page table are not set as read-only in the driver
> > DxeIplPeim, after the paging is setup. This might jeopardize the page table
> > integrity if there's buffer overflow occured in other part of system.
> >
> > This patch series will change this situation by clearing R/W bit in page attribute
> > of the pages used as page table.
> >
> > Validation works include booting Windows (10/server 2016) and Linux
> > (Fedora/Ubuntu) on OVMF and Intel real platform.
> >
> > Jian J Wang (4):
> >   MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
> >   MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
> >   MdeModulePkg/DxeIpl: Mark page table as read-only
> >   UefiCpuPkg/CpuDxe: Enable protection for newly added page table
> >
> >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
> >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
> >  MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
> >  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315
> > +++++++++++++++++++++-
> > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
> >  MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
> >  MdeModulePkg/MdeModulePkg.dec                    |  28 ++
> >  UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
> >  UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
> >  UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
> >  UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329
> > ++++++++++++++++++++++-
> >  UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
> >  12 files changed, 816 insertions(+), 13 deletions(-)  create mode 100644
> > MdeModulePkg/Include/Guid/PageTablePool.h
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel

Re: [PATCH v2 0/4] Enable page table write protection

[Yao, Jiewen]

Hi Jian
In V1 review, I suggest to test in UEFI shell env to make sure all page table is read only, with PageTable split in CPU driver.

May I know if that is done?

Thank you
Yao Jiewen

> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian J
> Wang
> Sent: Monday, December 4, 2017 4:36 PM
> To: edk2-devel@lists.01.org
> Subject: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> > v2 changes:
> >  a. Enable protection on any newly added page table after DxeIpl.
> >  b. Introduce page table pool concept to make page table allocation
> >     and protection easier and error free.
> 
> Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe.
> But the memory pages used for page table are not set as read-only in the driver
> DxeIplPeim, after the paging is setup. This might jeopardize the page table
> integrity if there's buffer overflow occured in other part of system.
> 
> This patch series will change this situation by clearing R/W bit in page attribute
> of the pages used as page table.
> 
> Validation works include booting Windows (10/server 2016) and Linux
> (Fedora/Ubuntu)
> on OVMF and Intel real platform.
> 
> Jian J Wang (4):
>   MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
>   MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
>   MdeModulePkg/DxeIpl: Mark page table as read-only
>   UefiCpuPkg/CpuDxe: Enable protection for newly added page table
> 
>  MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
>  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
>  MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
>  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315
> +++++++++++++++++++++-
>  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
>  MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
>  MdeModulePkg/MdeModulePkg.dec                    |  28 ++
>  UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
>  UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
>  UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
>  UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329
> ++++++++++++++++++++++-
>  UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
>  12 files changed, 816 insertions(+), 13 deletions(-)
>  create mode 100644 MdeModulePkg/Include/Guid/PageTablePool.h
> 
> --
> 2.14.1.windows.1
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel

Re: [PATCH v2 0/4] Enable page table write protection

[Wang, Jian J]

It's for sharing the pool between the DxeIpl and CpuDxe. If we don't care about 
wasting a little bit memory, it's ok to drop this definition. CpuDxe can reserve
a block of memory for page table for its own uses.

> -----Original Message-----
> From: Yao, Jiewen
> Sent: Tuesday, December 05, 2017 10:27 AM
> To: Wang, Jian J <jian.j.wang@intel.com>; Zeng, Star <star.zeng@intel.com>;
> edk2-devel@lists.01.org
> Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Dong, Eric <eric.dong@intel.com>
> Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> I do not suggest we define PAGE_TABLE_POOL_HEADER.
> If we can figure out other way, that will be better.
> 
> Thank you
> Yao Jiewen
> 
> 
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Monday, December 4, 2017 5:26 PM
> > To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org
> > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>;
> Dong,
> > Eric <eric.dong@intel.com>
> > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> >
> > That means we can't share page table pool between DxeIpl and CpuDxe. If this
> is
> > acceptable, I can remove them.
> >
> > > -----Original Message-----
> > > From: Zeng, Star
> > > Sent: Monday, December 04, 2017 5:11 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>;
> > Dong,
> > > Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> > >
> > > Recommend to not introduce the new header file and PCDs as new
> interfaces,
> > > but handle the page table pool separately in DxeIpl and CpuDxe.
> > >
> > > Thanks,
> > > Star
> > > -----Original Message-----
> > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Jian
> > J
> > > Wang
> > > Sent: Monday, December 4, 2017 4:36 PM
> > > To: edk2-devel@lists.01.org
> > > Subject: [edk2] [PATCH v2 0/4] Enable page table write protection
> > >
> > > > v2 changes:
> > > >  a. Enable protection on any newly added page table after DxeIpl.
> > > >  b. Introduce page table pool concept to make page table allocation
> > > >     and protection easier and error free.
> > >
> > > Write Protect feature (CR0.WP) is always enabled in driver
> > UefiCpuPkg/CpuDxe.
> > > But the memory pages used for page table are not set as read-only in the
> driver
> > > DxeIplPeim, after the paging is setup. This might jeopardize the page table
> > > integrity if there's buffer overflow occured in other part of system.
> > >
> > > This patch series will change this situation by clearing R/W bit in page
> attribute
> > > of the pages used as page table.
> > >
> > > Validation works include booting Windows (10/server 2016) and Linux
> > > (Fedora/Ubuntu) on OVMF and Intel real platform.
> > >
> > > Jian J Wang (4):
> > >   MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
> > >   MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
> > >   MdeModulePkg/DxeIpl: Mark page table as read-only
> > >   UefiCpuPkg/CpuDxe: Enable protection for newly added page table
> > >
> > >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
> > >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
> > >  MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
> > >  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315
> > > +++++++++++++++++++++-
> > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
> > >  MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
> > >  MdeModulePkg/MdeModulePkg.dec                    |  28 ++
> > >  UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
> > >  UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
> > >  UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
> > >  UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329
> > > ++++++++++++++++++++++-
> > >  UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
> > >  12 files changed, 816 insertions(+), 13 deletions(-)  create mode 100644
> > > MdeModulePkg/Include/Guid/PageTablePool.h
> > >
> > > --
> > > 2.14.1.windows.1
> > >
> > > _______________________________________________
> > > edk2-devel mailing list
> > > edk2-devel@lists.01.org
> > > https://lists.01.org/mailman/listinfo/edk2-devel

Re: [PATCH v2 0/4] Enable page table write protection

[Wang, Jian J]

I haven't got time to do it in automatic way. V1 may need a shell app to
check it, but current implementation might not need it because we now
have 2 or 3 continuous 2MB pages to hold all page tables. We just
need to verify the page attribute of those 2 or 3 page tables. It's easy
to do it in a JTAG debugger manually.

> -----Original Message-----
> From: Yao, Jiewen
> Sent: Tuesday, December 05, 2017 10:32 AM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Yao, Jiewen <jiewen.yao@intel.com>
> Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection
> 
> Hi Jian
> In V1 review, I suggest to test in UEFI shell env to make sure all page table is
> read only, with PageTable split in CPU driver.
> 
> May I know if that is done?
> 
> Thank you
> Yao Jiewen
> 
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Monday, December 4, 2017 4:36 PM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] [PATCH v2 0/4] Enable page table write protection
> >
> > > v2 changes:
> > >  a. Enable protection on any newly added page table after DxeIpl.
> > >  b. Introduce page table pool concept to make page table allocation
> > >     and protection easier and error free.
> >
> > Write Protect feature (CR0.WP) is always enabled in driver
> UefiCpuPkg/CpuDxe.
> > But the memory pages used for page table are not set as read-only in the
> driver
> > DxeIplPeim, after the paging is setup. This might jeopardize the page table
> > integrity if there's buffer overflow occured in other part of system.
> >
> > This patch series will change this situation by clearing R/W bit in page attribute
> > of the pages used as page table.
> >
> > Validation works include booting Windows (10/server 2016) and Linux
> > (Fedora/Ubuntu)
> > on OVMF and Intel real platform.
> >
> > Jian J Wang (4):
> >   MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid
> >   MdeModulePkg/PageTablePool.h: Page table pool GUID definition file
> >   MdeModulePkg/DxeIpl: Mark page table as read-only
> >   UefiCpuPkg/CpuDxe: Enable protection for newly added page table
> >
> >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.h            |  34 +++
> >  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf          |   3 +
> >  MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |   8 +-
> >  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315
> > +++++++++++++++++++++-
> >  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h |  15 ++
> >  MdeModulePkg/Include/Guid/PageTablePool.h        |  53 ++++
> >  MdeModulePkg/MdeModulePkg.dec                    |  28 ++
> >  UefiCpuPkg/CpuDxe/CpuDxe.c                       |  17 +-
> >  UefiCpuPkg/CpuDxe/CpuDxe.h                       |   2 +
> >  UefiCpuPkg/CpuDxe/CpuDxe.inf                     |   3 +
> >  UefiCpuPkg/CpuDxe/CpuPageTable.c                 | 329
> > ++++++++++++++++++++++-
> >  UefiCpuPkg/CpuDxe/CpuPageTable.h                 |  22 ++
> >  12 files changed, 816 insertions(+), 13 deletions(-)
> >  create mode 100644 MdeModulePkg/Include/Guid/PageTablePool.h
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel