From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 377AE2035625F for ; Tue, 5 Dec 2017 00:11:36 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2017 00:16:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,363,1508828400"; d="scan'208";a="9188398" Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.55]) by FMSMGA003.fm.intel.com with ESMTP; 05 Dec 2017 00:16:06 -0800 From: Jian J Wang To: edk2-devel@lists.01.org Date: Tue, 5 Dec 2017 16:16:02 +0800 Message-Id: <20171205081604.11644-1-jian.j.wang@intel.com> X-Mailer: git-send-email 2.15.1.windows.2 Subject: [PATCH v3 0/2] Enable page table write protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Dec 2017 08:11:37 -0000 > v3 changes: > a. According to code review comments, remove the public definitions of > page table pool. Now the DxeIpl and CpuDxe will have their own page > table pool but in the same mechanism. Related PCDs, GUDI and headers > are also removed. > b. Apply protection to all page tables, including new ones added in > CpuDxe driver. > c. Code/comments cleanup. > v2 changes: > a. Enable protection on any newly added page table after DxeIpl. > b. Introduce page table pool concept to make page table allocation > and protection easier and error free. Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe. But the memory pages used for page table are not set as read-only in the driver DxeIplPeim, after the paging is setup. This might jeopardize the page table integrity if there's buffer overflow occured in other part of system. This patch series will change this situation by clearing R/W bit in page attribute of the pages used as page table. Validation works include booting Windows (10/server 2016) and Linux (Fedora/Ubuntu) on OVMF and Intel real platform. Jian J Wang (2): MdeModulePkg/DxeIpl: Mark page table as read-only UefiCpuPkg/CpuDxe: Enable protection for newly added page table MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 34 +++ MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 8 +- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 301 ++++++++++++++++++++++- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 26 ++ UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +- UefiCpuPkg/CpuDxe/CpuDxe.h | 2 + UefiCpuPkg/CpuDxe/CpuPageTable.c | 226 ++++++++++++++++- UefiCpuPkg/CpuDxe/CpuPageTable.h | 34 +++ 8 files changed, 635 insertions(+), 13 deletions(-) -- 2.15.1.windows.2