From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A6DA22217CE42 for ; Wed, 6 Dec 2017 03:10:51 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id f206so6378289wmf.5 for ; Wed, 06 Dec 2017 03:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=yACwV6DseUv20iC9WY8DQBkZ1bFUhrHKD+CQxNUpuEvhG4GKDswv94rnC4g9hdZn90 e3hMx8Eu0BkXDZ3Fw/sfZWEIRj67LPrN14N0hXY+JXNAHaezmMjMO4olggXtxSFYKKk2 r8j8QSFsi/jHRIbxh3ywGCS5tQUiOsX44JrSuuTGff5NiVF8zQQxW+eY6qbJmdAogLpp /cB4voJyAff6RqIck/p7iGOwHhM89CHcvm4EKO4BMTEB5gF5WCw4x2nq82agzozS5/f3 oygFptHZgtHH9sGRi+MJRvzQfHOc2iw+n3jOmYsb2LFTxmAn7H+g7ff+ET4q0OdZCyU2 ymOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=GSaNx71ENqM9hXW5KJdpH04QpbfJ0B9SxA6BbjbVGN3Qyy8uGGX8o6DSK+wJ9magpT JYXay3aQv3Obfd7sZsFkVNmgZ1Rd5JD2/Xjz8KKQO80ObepVJmyJdP6O95W9KcMFnVcA wdR87kQrXEemMNaS6l4tOIF04W+ewWTq9A+mO2JvQU0c/TEyYg2DPvMD0dHKLz/nPyMR yv5EIYa2Nc2S1tHb6bNq2/ToZC3Q3EvvuPe03+D3sHIETV0Hr4Oh/WZ23BgJNRwgr/TF WWlmEQI+nBohVM0td3F50psWl4OcfRon6QWHC2UtUHYFDLyIFXMPzoDqYbr70iv4BITU JHcQ== X-Gm-Message-State: AJaThX5EfI/BNjbZ7bPtIfE3U5ow+PoW+ReC5f14Dfur6R2gPCAFdMik 6XHWY0stThU+AmIvoCj68HRW4TfHMrk= X-Google-Smtp-Source: AGs4zMb092QSHs8dvuPNr54fpQiD4zixIRyN0GuznlkUytjB2EuY3IE2J5zswlw/vxV1sxfz15AtBg== X-Received: by 10.80.168.162 with SMTP id k31mr25164307edc.253.1512558921921; Wed, 06 Dec 2017 03:15:21 -0800 (PST) Received: from localhost.localdomain ([84.203.69.204]) by smtp.gmail.com with ESMTPSA id b17sm1132422edj.21.2017.12.06.03.15.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Dec 2017 03:15:21 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com Date: Wed, 6 Dec 2017 11:15:06 +0000 Message-Id: <20171206111509.10144-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171206111509.10144-1-pete@akeo.ie> References: <20171206111509.10144-1-pete@akeo.ie> Subject: [PATCH v2 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Dec 2017 11:10:52 -0000 Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..2e508d6f1ad8 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ EXPORT CpuBreakpoint - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 320ac457ea3d..a81d56f61421 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -821,8 +821,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT - + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -831,7 +832,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT - + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC -- 2.9.3.windows.2