From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67D082217CE3E for ; Fri, 8 Dec 2017 06:02:38 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id b76so3414926wmg.1 for ; Fri, 08 Dec 2017 06:07:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=FwHuezrsaSixJpz/vICouhLAEeluEvfUeAAsenMqPq3XMHirsa3P9GHcGXDKVvKxFF eLIzSWlqn4feuZuY8sQ14CKJfOP+mh3GxHDHmTDvVD3HFSJeb5vMxxLFhIM3wv3nPvv9 kg5k/jKVbQcHCtYt+KLgcLi0SKQ1iaGjQw+kpby9Hkbf4vbOlg6eCCe+nYJdrB7UreXZ 3maDgyeACL1toVKI1t+/6h8I0UkNuZ6Pykyg6Yx0Fn78prpv6ww1jCPt8dTFeSmk3hph 8j5ErF8ojDv/58NnnhhchOLKk4/qKkZHChfeFhnzlwY1v4431OMgmCFDoFnD8szPTWkK z82Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=YExDs3ZVpj1pTXUL6Mw8Kp0qQdW0ycCjxSZcf8tRYo7D6V4LMqI4ru5/XFCles6t5Q 9TfB0Yim36vqLd88tVQRU9AC/biGf03JJFRduD89KnTc+Qlf09JgJHxhDZoxswHWr29t H4u5uMNfcaw8ytLlz7LNTqWn3Qmc+RxyPNa2aMpMFOP/zWUjLc3HRZCghF00AxNAGpnr T3/SYMwZ5x7q+35mucIbfySZ/fl9CdqRC9AY3r6U3OnR3WKITQN8/iCCWB0ic0SSxCIg JvmQWf+UF4uAo2wcXRO6Hhc2Erzfv2GBAkWGrY3jGuPC+etdcWKJ4rVvAXKxXxz79bam ViFA== X-Gm-Message-State: AJaThX6BEmGrBygcLMew4EwReYtyqOgb/rEMxlltv/hkeAhk56LgDtuc +zvPSUo2T3l00L8oie14nobDfs90nrg= X-Google-Smtp-Source: AGs4zMYs7eY9Kslj4pdHUo3Xju/M2wCBF9oW/Ui5RjXuRH6oKmMW8WavP7sE3uF9n5O49ylfMqjDDg== X-Received: by 10.80.204.197 with SMTP id b5mr50474222edj.249.1512742031189; Fri, 08 Dec 2017 06:07:11 -0800 (PST) Received: from localhost.localdomain ([84.203.66.92]) by smtp.gmail.com with ESMTPSA id c33sm3423442edd.36.2017.12.08.06.06.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 06:07:10 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com Date: Fri, 8 Dec 2017 14:06:28 +0000 Message-Id: <20171208140631.4252-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171208140631.4252-1-pete@akeo.ie> References: <20171208140631.4252-1-pete@akeo.ie> Subject: [PATCH v3 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Dec 2017 14:02:38 -0000 Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..2e508d6f1ad8 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ EXPORT CpuBreakpoint - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 320ac457ea3d..a81d56f61421 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -821,8 +821,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT - + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -831,7 +832,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT - + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC -- 2.9.3.windows.2