From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AB9112218E95F for ; Fri, 8 Dec 2017 10:23:05 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id v105so11640171wrc.3 for ; Fri, 08 Dec 2017 10:27:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=wI8JmBC8pbdk1dd9p/rz+ku/3SkUgT6Zfr8Rr4i2sO0=; b=QSSaKNwWAjXttDTr/AfmizVK67igmOx3+zMEB3Lm1TF9g0hmQsnFChEdNeApBvxrvQ AwwyQDXLbcqO2fI2yg/3JaI6bEnZzqCofgs5ozqJ+yg0/vvkeUlXKYDp4hhujRH8XKWf S3YacBmC6a4SXUOu5OUPXUkMEBaaFk3D2izbE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=wI8JmBC8pbdk1dd9p/rz+ku/3SkUgT6Zfr8Rr4i2sO0=; b=W2hr0TyLUxNgjt+Ej+32E/qHBMyrmBAUGk03W0jgJzTq8DHVQEvYK2yogOpJGD3/H5 UCJsJedD8Nt+wftQwlbUZgDVxsfOuve6bxJLGSDn33VicPmcD5XT1vTe11ZjergJ96t9 RaPnlPbJg19A5DghRVzDsCbW8L131f29PdaILS7ul2XucS+zUpgX1d9wCwKA8lChdZPF LZ8oOYA0HVEgnqC15BY/PYwagZX5AOA0xYhjiTADsCcw+0NgPg33F7gmzouL7Ifj6dBe AMuEkgqpfMgdtCge+vw8xzFo8LnHhCRF0ZDY80qsCKAY9oVzVLbP6pcYoRThw0SAUNqp JYnQ== X-Gm-Message-State: AJaThX7/EDebxmPmw158uKIHTJQWKKV9989CQoh2b5NrjweSr0Yyjr4j 4FmeK3csJVtcd+KnhW80/7hl1gSzZRk= X-Google-Smtp-Source: AGs4zMadPB0Dl5ii+1sToBl2SrDdz+jK3T7y/Lp9OKJX6ryFRMrdM8hFBZ3aIStmTELnTlCwaOOKEw== X-Received: by 10.223.132.129 with SMTP id 1mr26908848wrg.136.1512757658532; Fri, 08 Dec 2017 10:27:38 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id j59sm8849847wrj.77.2017.12.08.10.27.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 10:27:37 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Fri, 8 Dec 2017 18:27:32 +0000 Message-Id: <20171208182732.8891-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH] ArmPlatformPkg: retire obsolete PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Dec 2017 18:23:06 -0000 Retire a whole bunch of ArmPlatformPkg PCDs that are either related to the ARM BDS, to secure world execution or to stuff that has been migrated to edk2-platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dec | 41 -------------------- 1 file changed, 41 deletions(-) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index b33b6e630d85..7cec775abeee 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -45,13 +45,7 @@ [Guids.common] # gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } - gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } - [PcdsFeatureFlag.common] - # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. - gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 - - gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C @@ -60,18 +54,10 @@ [PcdsFeatureFlag.common] # we assume the OS will handle the FrameBuffer from the UEFI GOP information. gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D - # Enable Legacy Linux support in the BDS - gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E - [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 - # Stack for CPU Cores in Secure Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 - # Stack for CPU Cores in Non Secure Mode gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 @@ -80,9 +66,6 @@ [PcdsFixedAtBuild.common] # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 - # Boot Monitor FileSystem - gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A - # # ARM Primecells # @@ -114,33 +97,9 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 - # - # BDS - Boot Manager - # - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019 - gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C - gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F - - gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B - gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C - [PcdsFixedAtBuild.common,PcdsDynamic.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033 - -[PcdsFixedAtBuild.ARM] - # Stack for CPU Cores in Secure Monitor Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 - -[PcdsFixedAtBuild.AARCH64] - # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. - # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize - # and PcdCPUCoreSecSecondaryStackSize - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 - -- 2.11.0