From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 14EA42214E323 for ; Mon, 11 Dec 2017 07:37:30 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id o2so18050818wro.5 for ; Mon, 11 Dec 2017 07:42:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EKQLI/CQYcfB+y8bIAYOUp64Sfq+0bAuHYJ7hxuG6zI=; b=HNYsE+cIBPaQW3Rdz8Lo6fZNpJlHP474b1x7qWzZLZ46I87EAYTnI4fkYmcArPNIFQ tenxU6qYcBNVMNLc5u+eLUfc66kdYt4ccqlbv8GaYBjnZ38zhUi7haQ9Rn0J05RXCNvQ iOYljONfYhS6QdtQbVFdny3SgzrfWOvAa6tmc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EKQLI/CQYcfB+y8bIAYOUp64Sfq+0bAuHYJ7hxuG6zI=; b=GNK7j9/6wMkYQatLX7SnVtYMrUCpX3pZeX+drIcYky5DkUucRWg6DZywzn8aGh/bOq BiDl+HXvlZaDwAqxnF9K1jLLwB791U7TRDvHqYL0v3Dd47L+s3NntMtcwq0LPYdAEO2p Je2KHBPUj3tIunTDAKXflMBoKxoxKBhH9jsu82U1BzHrtUlnDZJLVEIodDC67k6oo6xp wPWz+LTvmJTiSerqJCHYuTVVRHI1SG+ocXiHXHYsrFIVdzGvSq23mULGItF6naiy5505 rIxI0JIPpfSJl9AnozT7r5RyAuK0X8cP1fNRAdrjF0DRloqOzzzhdX82Hi3T48L9I2nh riVA== X-Gm-Message-State: AKGB3mKajDIzPDz3ECy4SPEomW0Qn7qi/sjyZTaNvqUlNkURMJc62zTf +oLGEwVE8G9ozSUQtSX3AYwOSg== X-Google-Smtp-Source: ACJfBour+J5JcPIVGXMA4BIiBLJtAuquEXSFz0+nhIEJMq6gepZem+gd0JdwU/gLoe64EWzG39HTHg== X-Received: by 10.223.134.230 with SMTP id 35mr753346wry.74.1513006926936; Mon, 11 Dec 2017 07:42:06 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id d1sm15986795wra.44.2017.12.11.07.42.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Dec 2017 07:42:06 -0800 (PST) Date: Mon, 11 Dec 2017 15:42:04 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20171211154204.lcdzebwhub6yiwy6@bivouac.eciton.net> References: <20171208182732.8891-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171208182732.8891-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] ArmPlatformPkg: retire obsolete PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Dec 2017 15:37:31 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Dec 08, 2017 at 06:27:32PM +0000, Ard Biesheuvel wrote: > Retire a whole bunch of ArmPlatformPkg PCDs that are either related > to the ARM BDS, to secure world execution or to stuff that has been > migrated to edk2-platforms. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Commenting out-of-order... By the time we get to this, should we not also delete ## PL111 Lcd & HdLcd gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 ? > --- > ArmPlatformPkg/ArmPlatformPkg.dec | 41 -------------------- > 1 file changed, 41 deletions(-) > > diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec > index b33b6e630d85..7cec775abeee 100644 > --- a/ArmPlatformPkg/ArmPlatformPkg.dec > +++ b/ArmPlatformPkg/ArmPlatformPkg.dec > @@ -45,13 +45,7 @@ [Guids.common] > # > gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } > > - gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } > - > [PcdsFeatureFlag.common] > - # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. > - gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 > - > - gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 > gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 > > gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C > @@ -60,18 +54,10 @@ [PcdsFeatureFlag.common] > # we assume the OS will handle the FrameBuffer from the UEFI GOP information. > gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D > > - # Enable Legacy Linux support in the BDS > - gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E > - > [PcdsFixedAtBuild.common] > gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 > gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 > > - # Stack for CPU Cores in Secure Mode > - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005 > - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 > - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 > - > # Stack for CPU Cores in Non Secure Mode > gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 > gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 > @@ -80,9 +66,6 @@ [PcdsFixedAtBuild.common] > # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) > gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 > > - # Boot Monitor FileSystem > - gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A > - > # > # ARM Primecells > # > @@ -114,33 +97,9 @@ [PcdsFixedAtBuild.common] > gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 > gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 > > - # > - # BDS - Boot Manager > - # > - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019 > - gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C > - gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D > - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F > - > - gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B > - gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C > - > [PcdsFixedAtBuild.common,PcdsDynamic.common] > ## PL031 RealTimeClock > gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 > gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 > > gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033 > - > -[PcdsFixedAtBuild.ARM] > - # Stack for CPU Cores in Secure Monitor Mode > - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 > - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 > - > -[PcdsFixedAtBuild.AARCH64] > - # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. > - # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize > - # and PcdCPUCoreSecSecondaryStackSize > - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 > - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 > - > -- > 2.11.0 >