From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AEBB421A1099A for ; Tue, 12 Dec 2017 02:33:38 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id k61so20570231wrc.4 for ; Tue, 12 Dec 2017 02:38:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=bqHwrkRACWODM/6MXPflNi0U3dYyAmkMsJo3n20cmA4=; b=FncrBO0PHj9OY3sFVY80KfSx9cmaf64cOML9LaECf7k3/ros6u8yAw473v09+yaLNC ZAgBRqFby4HA0wNRtqsK+X+i6cmEr4lGMTEJlaVBuDmmBrpzesQ91sGuU1wQLimatDEJ uxHLGFGeZNDx7nahpWQyYtffTHrQI03lf5vuM= X-Google-DKIM-Signature: v=1; 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Tue, 12 Dec 2017 02:38:14 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel Date: Tue, 12 Dec 2017 10:37:59 +0000 Message-Id: <20171212103807.18836-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH edk2-platforms 0/8] SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 10:33:39 -0000 A round of updates for Socionext SynQuacer: - enable CPU idle states in the DT, so that the OS can put cores to sleep using PSCI (#1) - add the build number to PCDs that end up in user visible strings (#2) - fix a PCIe detection issue in the DeveloperBox x16 slot, by keeping PERST# asserted for at least 100 ms before link training (#3) - ignore PCIe RC #0 if no card is inserted on EVB (#4 - #6) - add the secondary UART to the DT for the OS to use (this is UART #0 on the LS connector on DeveloperBox) (#7) - explicitly retrain the downstream links on the Asmedia 1182/1184 PCIe switch, to enable Gen2 speeds Ard Biesheuvel (7): Silicon/SynQuacer: enable CPU idle states in device tree Platform/Socionext/SynQuacer: expose build number as firmware version Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting Silicon/SynQuacer: disable PCI RC #0 DT node if disabled Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed Masahisa KOJIMA (1): Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 16 ++- Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 18 ++- Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 57 ++++---- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 94 +++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 42 ++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 4 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 58 +++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 +++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + 19 files changed, 504 insertions(+), 88 deletions(-) create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf -- 2.11.0