From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 167D621B02832 for ; Tue, 12 Dec 2017 02:33:44 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id q9so20586997wre.7 for ; Tue, 12 Dec 2017 02:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=V76rLpFzrLbqwjRVFGpH647CQ9PpSP7JdZcdJcosC7vh0fFWIiWuwse1sgP+Dd3jtx r1deuKI3yUiLfVyO5fJ9Al0ixVnlJuDPJVKiFrlYWm+LGd3eDs9SUxKalYpfMfZ37jU8 ZLvxaaZKUMbzasQQGpggL6RLec9Eif5+PVlAE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=OV4TrV9G6reN4A/rJRxieqxhwbyjHSz4tFetddDca1WmXWC3tMe8QvugYTuiCm6yNs IlILNss1tn/d1qDedeWS5SHoQ5/RDmx25BJI0g4TRE6a7J54G7x/WBZLMSm0qj+vlvgW RVvuDuugdLAhY0QcHrKa2b/XgNPflCf0PrtgfglwLVWiQt4b8/IcdAmc9rI/ilyVDyc2 Gbsm67WcABYDfvX6j8GgmYzGxdBbgpxpDoOscvn5bk9uf5h0rdnGrbySkGw8qVmaGen/ sJqxyJG9kSeOpvEIsO4ZFQs/pI/ooZN+r66VQqX/dFz65EOCJLzKXKR8JnLPXPl4k1xr W5wA== X-Gm-Message-State: AKGB3mLtOdAK6COmya9ALLDffPmMCkHrK0GZEmtgSShChhNC/o5eGqLS yeaLYoLWVtGySjD+kjxurrN8hZKdZ+g= X-Google-Smtp-Source: ACJfBotq0RvVTurgVdbrIR/9RrGE3AkzIshyAkQ/0WCxX+1BtZzFIDIOcCmJ7BBD5mH+KU1EEO1KxQ== X-Received: by 10.223.136.38 with SMTP id d35mr3439705wrd.36.1513075101897; Tue, 12 Dec 2017 02:38:21 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:21 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel Date: Tue, 12 Dec 2017 10:38:02 +0000 Message-Id: <20171212103807.18836-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 10:33:45 -0000 Attempt to adhere more closely to the PCIe spec by ensuring that PERST# remains asserted for at least 100 ms. Give it a good margin, and delay for 150 ms; the additional boot time delay is not going to be noticeable by anyone anyway. So split the init routine in a pre and post part, and put the delay in the middle so we only need to do it once. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 1 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 46 +++++++++++++++----- 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 08484f4f8b1a..5d87727c73ba 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + UefiBootServicesTableLib [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e63b3a4bb23b..3da94945f96a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -176,6 +177,8 @@ SnPcieSetData ( } MmioWrite32 (Base + Offset, Data); + + ArmDataMemoryBarrier (); } STATIC @@ -194,6 +197,8 @@ SnPcieReadData ( Shift++; } + ArmDataMemoryBarrier (); + return (MmioRead32 (Base + Offset) >> Shift) & Mask; } @@ -219,12 +224,8 @@ SnDbiRoWrEn ( STATIC VOID -PciInitController ( - IN EFI_PHYSICAL_ADDRESS ExsBase, - IN EFI_PHYSICAL_ADDRESS DbiBase, - IN EFI_PHYSICAL_ADDRESS ConfigBase, - IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge +PciInitControllerPre ( + IN EFI_PHYSICAL_ADDRESS ExsBase ) { SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0); @@ -256,7 +257,18 @@ PciInitController ( // 3: Set device_type (RC) SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4); +} +STATIC +VOID +PciInitControllerPost ( + IN EFI_PHYSICAL_ADDRESS ExsBase, + IN EFI_PHYSICAL_ADDRESS DbiBase, + IN EFI_PHYSICAL_ADDRESS ConfigBase, + IN EFI_PHYSICAL_ADDRESS IoMemBase, + IN CONST PCI_ROOT_BRIDGE *RootBridge + ) +{ // 4: Set Bifurcation 1=disable 4=able // 5: Supply Reference (It has executed) // 6: Wait for 10usec (Reference Clocks is stable) @@ -389,11 +401,23 @@ SynQuacerPciHostBridgeLibConstructor ( } for (Idx = 0; Idx < Count; Idx++) { - PciInitController (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } + + // + // The PCIe spec requires that PERST# is asserted for at least 100 ms after + // the power and clocks have become stable. So let's give a bit or margin, + // and stall for 150 ms between asserting PERST# on both controllers and + // de-asserting it again. + // + gBS->Stall (150 * 1000); + + for (Idx = 0; Idx < Count; Idx++) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &RootBridges[Idx]); } return EFI_SUCCESS; -- 2.11.0