From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org
Cc: leif.lindholm@linaro.org, daniel.thompson@linaro.org,
masami.hiramatsu@linaro.org,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH edk2-platforms 6/8] Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected
Date: Tue, 12 Dec 2017 10:38:05 +0000 [thread overview]
Message-ID: <20171212103807.18836-7-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org>
The EVB does not boot if PCI RC #0 has no card inserted, and will hang in
the PCIe initialization code. So let's check the presence detect GPIO,
and only enable PCI RC #0 if it is asserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 ++++++++++++++------
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 +
Silicon/Socionext/SynQuacer/SynQuacer.dec | 1 +
4 files changed, 59 insertions(+), 21 deletions(-)
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index c71425664bdc..917632c2b4c1 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -374,6 +374,10 @@ [PcdsFixedAtBuild.common]
# set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0
+ # On the EVB, PCIe RC #0 should not be enabled from software if no card
+ # was inserted, or the boot will hang.
+ gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|15
+
!if $(BUILD_NUMBER) > 1
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER)"
!endif
@@ -395,6 +399,9 @@ [PcdsDynamicDefault]
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF
+ # enable RC #1 only by default, RC #0 will be enabled if an endpoint is detected
+ gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x2
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
index e4aec8b09169..7c529a22c6ef 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
@@ -24,7 +24,10 @@
#include <Ppi/EmbeddedGpio.h>
#include <Ppi/MemoryDiscovered.h>
-#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8
+#define GPIO_NOT_IMPLEMENTED MAX_UINT8
+
+#define CLEAR_SETTINGS_GPIO_ASSERTED 1
+#define PCIE_GPIO_CARD_PRESENT 0
STATIC
CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase);
@@ -100,6 +103,35 @@ STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescriptor = {
&mDramInfoPpi
};
+STATIC
+EFI_STATUS
+ReadGpioInput (
+ IN EMBEDDED_GPIO_PPI *Gpio,
+ IN UINT8 Pin,
+ OUT UINTN *Value
+ )
+{
+ EFI_STATUS Status;
+
+ if (Pin == GPIO_NOT_IMPLEMENTED) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to set GPIO %d as input - %r\n",
+ __FUNCTION__, Pin, Status));
+ return Status;
+ }
+
+ Status = Gpio->Get (Gpio, Pin, Value);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to get GPIO %d state - %r\n",
+ __FUNCTION__, Pin, Status));
+ }
+ return Status;
+}
+
EFI_STATUS
EFIAPI
PlatformPeim (
@@ -109,30 +141,26 @@ PlatformPeim (
EMBEDDED_GPIO_PPI *Gpio;
EFI_STATUS Status;
UINTN Value;
- UINT8 Pin;
ASSERT (mDramInfo->NumRegions > 0);
- Pin = FixedPcdGet8 (PcdClearSettingsGpioPin);
- if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) {
- Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL,
- (VOID **)&Gpio);
- ASSERT_EFI_ERROR (Status);
+ Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL,
+ (VOID **)&Gpio);
+ ASSERT_EFI_ERROR (Status);
- Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n",
- __FUNCTION__, Status));
- } else {
- Status = Gpio->Get (Gpio, Pin, &Value);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n",
- __FUNCTION__, Status));
- } else if (Value > 0) {
- DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__));
- PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS);
- }
- }
+ Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdClearSettingsGpioPin), &Value);
+ if (!EFI_ERROR (Status) && Value == CLEAR_SETTINGS_GPIO_ASSERTED) {
+ DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__));
+ PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS);
+ }
+
+ Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdPcie0PresenceDetectGpioPin),
+ &Value);
+ if (!EFI_ERROR (Status) && Value == PCIE_GPIO_CARD_PRESENT) {
+ DEBUG ((DEBUG_INFO,
+ "%a: card detected in PCIe RC #0, enabling\n", __FUNCTION__));
+ Status = PcdSet8S (PcdPcieEnableMask, PcdGet8 (PcdPcieEnableMask) | BIT0);
+ ASSERT_EFI_ERROR (Status);
}
//
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
index a6501fb205e1..eb6a5bf9ac1a 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
@@ -43,6 +43,7 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdFvSize
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin
gSynQuacerTokenSpaceGuid.PcdDramInfoBase
+ gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin
[Ppis]
gEdkiiEmbeddedGpioPpiGuid ## CONSUMES
@@ -51,6 +52,7 @@ [Ppis]
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
+ gSynQuacerTokenSpaceGuid.PcdPcieEnableMask
[Depex]
gEdkiiEmbeddedGpioPpiGuid
diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec
index 2e18cb33346d..a21f12b5bc32 100644
--- a/Silicon/Socionext/SynQuacer/SynQuacer.dec
+++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec
@@ -36,6 +36,7 @@ [PcdsFixedAtBuild]
# GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004
+ gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|0xFF|UINT8|0x00000006
gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005
--
2.11.0
next prev parent reply other threads:[~2017-12-12 10:33 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-12 10:37 [PATCH edk2-platforms 0/8] SynQuacer updates Ard Biesheuvel
2017-12-12 10:38 ` [PATCH edk2-platforms 1/8] Silicon/SynQuacer: enable CPU idle states in device tree Ard Biesheuvel
2017-12-12 10:38 ` [PATCH edk2-platforms 2/8] Platform/Socionext/SynQuacer: expose build number as firmware version Ard Biesheuvel
2017-12-12 18:17 ` Leif Lindholm
2017-12-12 18:20 ` Ard Biesheuvel
2017-12-12 18:24 ` Leif Lindholm
2017-12-12 18:28 ` Ard Biesheuvel
2017-12-12 18:33 ` Leif Lindholm
2017-12-12 10:38 ` [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# Ard Biesheuvel
2017-12-12 17:24 ` Leif Lindholm
2017-12-12 10:38 ` [PATCH edk2-platforms 4/8] Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting Ard Biesheuvel
2017-12-12 10:38 ` [PATCH edk2-platforms 5/8] Silicon/SynQuacer: disable PCI RC #0 DT node if disabled Ard Biesheuvel
2017-12-12 14:54 ` Ard Biesheuvel
2017-12-12 17:32 ` Leif Lindholm
2017-12-12 17:35 ` Ard Biesheuvel
2017-12-12 17:50 ` Leif Lindholm
2017-12-12 18:09 ` Ard Biesheuvel
2017-12-12 18:15 ` Leif Lindholm
2017-12-12 10:38 ` Ard Biesheuvel [this message]
2017-12-12 10:38 ` [PATCH edk2-platforms 7/8] Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS Ard Biesheuvel
2017-12-12 17:37 ` Leif Lindholm
2017-12-12 10:38 ` [PATCH edk2-platforms 8/8] Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed Ard Biesheuvel
2017-12-12 17:47 ` Leif Lindholm
2017-12-12 17:51 ` Ard Biesheuvel
2017-12-12 18:15 ` Leif Lindholm
2017-12-12 18:20 ` [PATCH edk2-platforms 0/8] SynQuacer updates Leif Lindholm
2017-12-12 18:38 ` Ard Biesheuvel
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