From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA69F21A1099A for ; Tue, 12 Dec 2017 09:20:10 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id b76so195716wmg.1 for ; Tue, 12 Dec 2017 09:24:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EfzaG/pYSZOcPOrLwKXEOmK0X4+F4e6TKIzmKX6TfUg=; b=P0BcmtmKcz7HkioPDpTth+gZM4AeFPGfWCVJ0+Hotdx/KrMp4JBiwlxUZUDbe2xypQ wLnZ9mzuiUf1LXdDWD9tzO/1dvtG3ZUqt7Sqli2KAY5NkvIoKr8v9fP0KYY+ysTqqev3 r10CF5HmQpBlYgokJC8b9ATfE05+DgSGvp/2w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EfzaG/pYSZOcPOrLwKXEOmK0X4+F4e6TKIzmKX6TfUg=; b=Z0RrlNWYaypDu309dj9tUkWV4vryN2O2Zrnizhnd4skU6TRZWHiINItKOBLrr+y1oH mubo1vjSv3gcc1gwuft/tYPawt+V2Du8DbEZZSLTKoElNJIgzwHTGg6cIbB9isiZ84xu YPJoE8ELAGoC0zdTTvaKClBGB5tMMsjvaMdnGe0N+SLUurvDMDuB0AiEgFIwx0+eUunz IqFC9eIjZC+ZYYZ0N9//YkCdD/hK0SPwX6oFK665bYRck6CZ5uA/bpB5kxlecBNbIFtT kLH49wSTfX8fvjxTXXtO2W0d81QCko8LMmh6mxKvYqxkgMfTYDp8HFpbbdyeAKMGYo1l 6xVQ== X-Gm-Message-State: AKGB3mL7GfqB+Ek1ZjDE59PpFfVvc1T82JsRhk8rznnY5R/c8IH9TNRQ PYTl/gQUBIF7lZJhAeJwaLhplQ== X-Google-Smtp-Source: ACJfBovQZbzJ3uMMazSK4aDY5sOMJ8otJq6ezYcw+VA4/EuGpkC1jEDDsp3wj3y90c33BGSkyTJM6g== X-Received: by 10.28.238.135 with SMTP id j7mr2574781wmi.140.1513099488165; Tue, 12 Dec 2017 09:24:48 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n17sm18459082wrg.94.2017.12.12.09.24.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2017 09:24:47 -0800 (PST) Date: Tue, 12 Dec 2017 17:24:45 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171212172445.5n4dyi7tfvpazav3@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> <20171212103807.18836-4-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171212103807.18836-4-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 17:20:11 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Dec 12, 2017 at 10:38:02AM +0000, Ard Biesheuvel wrote: > Attempt to adhere more closely to the PCIe spec by ensuring that PERST# > remains asserted for at least 100 ms. Give it a good margin, and delay > for 150 ms; the additional boot time delay is not going to be noticeable > by anyone anyway. > > So split the init routine in a pre and post part, and put the delay in > the middle so we only need to do it once. > This patch also adds two missing memory barriers. Please add this to commit message. If you do: Reviewed-by: Leif Lindholm > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 1 + > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 46 +++++++++++++++----- > 2 files changed, 36 insertions(+), 11 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf > index 08484f4f8b1a..5d87727c73ba 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf > @@ -45,6 +45,7 @@ [LibraryClasses] > DebugLib > DevicePathLib > MemoryAllocationLib > + UefiBootServicesTableLib > > [FixedPcd] > gArmTokenSpaceGuid.PcdPciIoTranslation > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index e63b3a4bb23b..3da94945f96a 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -176,6 +177,8 @@ SnPcieSetData ( > } > > MmioWrite32 (Base + Offset, Data); > + > + ArmDataMemoryBarrier (); > } > > STATIC > @@ -194,6 +197,8 @@ SnPcieReadData ( > Shift++; > } > > + ArmDataMemoryBarrier (); > + > return (MmioRead32 (Base + Offset) >> Shift) & Mask; > } > > @@ -219,12 +224,8 @@ SnDbiRoWrEn ( > > STATIC > VOID > -PciInitController ( > - IN EFI_PHYSICAL_ADDRESS ExsBase, > - IN EFI_PHYSICAL_ADDRESS DbiBase, > - IN EFI_PHYSICAL_ADDRESS ConfigBase, > - IN EFI_PHYSICAL_ADDRESS IoMemBase, > - IN CONST PCI_ROOT_BRIDGE *RootBridge > +PciInitControllerPre ( > + IN EFI_PHYSICAL_ADDRESS ExsBase > ) > { > SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0); > @@ -256,7 +257,18 @@ PciInitController ( > > // 3: Set device_type (RC) > SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4); > +} > > +STATIC > +VOID > +PciInitControllerPost ( > + IN EFI_PHYSICAL_ADDRESS ExsBase, > + IN EFI_PHYSICAL_ADDRESS DbiBase, > + IN EFI_PHYSICAL_ADDRESS ConfigBase, > + IN EFI_PHYSICAL_ADDRESS IoMemBase, > + IN CONST PCI_ROOT_BRIDGE *RootBridge > + ) > +{ > // 4: Set Bifurcation 1=disable 4=able > // 5: Supply Reference (It has executed) > // 6: Wait for 10usec (Reference Clocks is stable) > @@ -389,11 +401,23 @@ SynQuacerPciHostBridgeLibConstructor ( > } > > for (Idx = 0; Idx < Count; Idx++) { > - PciInitController (mBaseAddresses[Idx].ExsBase, > - mBaseAddresses[Idx].DbiBase, > - mBaseAddresses[Idx].ConfigBase, > - mBaseAddresses[Idx].IoMemBase, > - &RootBridges[Idx]); > + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); > + } > + > + // > + // The PCIe spec requires that PERST# is asserted for at least 100 ms after > + // the power and clocks have become stable. So let's give a bit or margin, > + // and stall for 150 ms between asserting PERST# on both controllers and > + // de-asserting it again. > + // > + gBS->Stall (150 * 1000); > + > + for (Idx = 0; Idx < Count; Idx++) { > + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, > + mBaseAddresses[Idx].DbiBase, > + mBaseAddresses[Idx].ConfigBase, > + mBaseAddresses[Idx].IoMemBase, > + &RootBridges[Idx]); > } > > return EFI_SUCCESS; > -- > 2.11.0 >