From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9CDE21B02821 for ; Tue, 12 Dec 2017 09:33:24 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id i11so239103wmf.4 for ; Tue, 12 Dec 2017 09:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=d3Iv4s2pN5HYwSkxvI2iU4fBYVKFBzKtsLCWxgfEb6s=; b=LcR1YxZlWbjwF0OPetdb4K4tSnVzt7kepTbnolIz3ngj7bJslGpoIqX9p7lBkx1p6y nLs108fW3VIZ0BLwTC2X7492vIFpjOuH7K2bvWcm0WPb8WgZF3zQKcl3SHHCA/yfP9Ob v6zrcndVE1M3vNtO+1yeL9dG9+Sz0VUZOTHa8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=d3Iv4s2pN5HYwSkxvI2iU4fBYVKFBzKtsLCWxgfEb6s=; b=cf/4U0OuazPTBQbluAUwWC2HAIixx816OCst0ck6pf8uKIQfeUNdtv44M8b813TRnS 04aKGX7KGiQnYwabZKugSFVXtNcpYvRlS0L5UAmMoaSEOUl9lvSfVsMwBZi1ZTp+I89m /h1rKbg9XiI79LrQOhbktNFdX6DwKGjAojkTkBM3Vfmw7W4gQsFi2q07Im53whBUIr1h maZ5i7QW8zzChI/cyeSbTAo3lDjmOfN40bm9/WFjeNZ5yv20DDSulJud4lxO3pVVhtYh Mc9hR4kiiJScrOIqG67N7dWBFIp5bnhrkM+uy6qHITNWsXBIoMH3r7r/e8sOqxPdsCT8 UcHw== X-Gm-Message-State: AKGB3mKHPujvvL116uGMB2FzbtBEj/zaY6yE+UL7sLlOEVNGNq3KzViV qQ/Zt4gVlYOHv8r1kI+TGh+/wA== X-Google-Smtp-Source: ACJfBosuFcTN3u1C3bsUYIu8jROu4iOxBaWYPUBr8vv6c0xvJL4OmLt4VpOpC3IhX6a+HXGRDRGRxw== X-Received: by 10.28.147.84 with SMTP id v81mr2497003wmd.133.1513100282432; Tue, 12 Dec 2017 09:38:02 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id d23sm55750wma.48.2017.12.12.09.38.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2017 09:38:01 -0800 (PST) Date: Tue, 12 Dec 2017 17:37:59 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Masahisa KOJIMA Message-ID: <20171212173759.3xshy2h6y2apy2xj@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> <20171212103807.18836-8-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171212103807.18836-8-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 7/8] Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 17:33:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Suggested subject tweak: Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the OS -> Silicon/Socionext/SynQuacer: add UART #0 node to DT with that: Reviewed-by: Leif Lindholm On Tue, Dec 12, 2017 at 10:38:06AM +0000, Ard Biesheuvel wrote: > From: Masahisa KOJIMA > > In order to be able to use UART #0 on the DeveloperBox's 96boards low > speed connector, expose it to the OS by adding a node to the device > tree. This requires a CM3 firmware build that makes the SCP detach > from the serial port after boot. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Masahisa KOJIMA > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index c9fee5d1f350..37a3981f0360 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -440,6 +440,15 @@ > clock-names = "uartclk", "apb_pclk"; > }; > > + fuart: fuart@51040000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x51040000 0x0 0x1000>; > + interrupts = ; > + clock-frequency = <62500000>; > + reg-io-width = <4>; > + reg-shift = <2>; > + }; > + > clk_netsec: refclk125mhz { > compatible = "fixed-clock"; > clock-frequency = <125000000>; > -- > 2.11.0 >