From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A7EAB21A1099A for ; Tue, 12 Dec 2017 10:10:53 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id t8so447857wmc.3 for ; Tue, 12 Dec 2017 10:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=kPYSXykCMpep0znT3MaFxoWmERDqCDF2mX0mAKVVun8=; b=KkI3hQZduIi+b5cTtoWbR+lq+rrNP3jIWgvoeQLUG2xvl3p2dilcXQxb10+Y+QUfPX 5BEI55WidnpAEnO8aW+/dfndLU4lXetg67YXZzlgnM07Yk8JMRI8vtBJbZaWnWg4UyEV ST8sDUhe+Wp/j4ayR790S8sWAlzXTFQLca7Xc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=kPYSXykCMpep0znT3MaFxoWmERDqCDF2mX0mAKVVun8=; b=JnETxjI1yNxyQHzLpz4EPtddbHbQz45IdiFp+Se3i6cbJxqMDYaESU44P2gQVqgLbD fV/mbDxeirERLwc7fG/EdbVcaa0DKiu1dqEFZ97lAbCbhB1iOUZ+TsSU2cr050bBBBrd 739mJ1dMKxa1eR+iD84qbRmPK3cCY/S7yOEdJFS6QKvRKLuObHQJ2phnM/SvBMeX6Lq1 i8UizLv8CDGch34VXT7tdDJH7GBEASNmpGxJ+KWwYShdsdHRR8PXD3UtimbKzydszGhO 2dIEk9NW+knxe4Qxii6COGTb9dwJc0TntoG/aqr5b4CA4pOo4iBzTHmcvgBOnRwXCujG kr+A== X-Gm-Message-State: AKGB3mINi2RNOgXFDp2OuTXIf299ux1HZNcMZFfe0BfDbxMgYMJl3TyO e0cOwXXZWsO6zWD/Kou/r1H61Q== X-Google-Smtp-Source: ACJfBosBIA9DfEst/FV50PZFtI2NnWAvPalxUaYjB0qqZ+2Rvf+xT8YyvMfK/8UrGLQETEStl0P5nw== X-Received: by 10.28.87.207 with SMTP id l198mr2403371wmb.45.1513102531041; Tue, 12 Dec 2017 10:15:31 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b16sm22513678wrd.69.2017.12.12.10.15.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2017 10:15:29 -0800 (PST) Date: Tue, 12 Dec 2017 18:15:28 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu Message-ID: <20171212181528.y7ujva22tzuo5nku@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> <20171212103807.18836-9-ard.biesheuvel@linaro.org> <20171212174718.mbbrhh7opjbqmxs6@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 8/8] Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 18:10:54 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Dec 12, 2017 at 05:51:18PM +0000, Ard Biesheuvel wrote: > On 12 December 2017 at 17:47, Leif Lindholm wrote: > > On Tue, Dec 12, 2017 at 10:38:07AM +0000, Ard Biesheuvel wrote: > >> For some reason, the Asmedia 118x PCIe switch needs a little help to > >> make sure that the downstream links train at Gen2 speed. So add a > >> PCI I/O protocol notifier that implements this for each PCIe downstream > >> port that is present on the system. > >> > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel > >> --- > >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ > >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- > >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ > >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + > >> 4 files changed, 184 insertions(+), 9 deletions(-) > >> > >> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c > >> new file mode 100644 > >> index 000000000000..b069b42d0a42 > >> --- /dev/null > >> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c > > > > Bikeshedding time: > > This driver would likely be needed for any other platform including > > this switch as well, right? > > > > While it may be premature to create a standalone driver under > > Silicon/Asmedia ... how about calling this file something to make it > > clear that it is specifically intended to handle Asmedia 118x devices, > > to make it easier* to do so in the future? I.e. Asmedia118x.c? > > > > * by avoiding accruing other random bits of platform-specific PCI > > hackery in the same file. > > > > To be honest, I am not entirely sure. I need this hack for the > standalone card as well as the onboard switch, so it is not related to > a board level defect on developerbox. However, it could be related to > how the Synopsys IP manages the reset and training etc. > > But I agree, let's move this to Asmedia118x.c and not create a generic > looking file that invites more PCI quirks to be parked there With that: Reviewed-by: Leif Lindholm