From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 06E8221A1099A for ; Tue, 12 Dec 2017 10:16:23 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id t8so477279wmc.3 for ; Tue, 12 Dec 2017 10:21:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Z87he+PAN5AhHMegk1sAcGJK3LiFP1MKapjJCeZyJmg=; b=Jb3XtCTwXvaXpfFhEX8YT5V9i+gwQl+VQRh0e1+Wi4PqCmDZpFj387DhBA11BALzUm 3JUhbpJSccYZAhXn5JiSJSxLEelZLtL5fmJIqfExqS0UrlEcnUvX7/QOzYasEbA20XWy 6EYtm5WmFCOkz8UXqBPE0yHur9vtJmznVnMQo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Z87he+PAN5AhHMegk1sAcGJK3LiFP1MKapjJCeZyJmg=; b=UTZPq+uK7pPY8CMgGL3o4QJoWghx3fBcVQvoR24JUB6O0UEnSrLqGubsTqXOMp61Nh GW+jXq2a+ABnFMpMO9FKx0RZXVzCEyYn+XZLUiXky49NOiIafJa+LU1nNmuHI2NLIRn0 J+jnGGX6nfj0BEzGcb8XstCZnqImVYt+MelkEm4fhu+BUvNQno+rkcyEMb78tfw7EAZQ 0zERkiXMyeBcXKTQh8IbomuF+1FuG0CTPR1nRXPRjknUIJd9gv1TL3FUziAo/8bZSTFU fIlzeGcjk8DvzruxBnjX/WOzQWQdIC6Kr3qBgXypc1ynLgW4H7SYmIJ5QxXOnYLs9gFF RD4A== X-Gm-Message-State: AKGB3mJuXNjXL75ZtiGd0uAD1r71ere610TyOmPDpyaFLQVIRS9KaLyS G4uqGZR6fU11ZNvl/2Hjpw4qzg== X-Google-Smtp-Source: ACJfBospxH2RwU988dKYoabrjfGYyGDWfC5AELDBASPxAV385qUbUDMlFKyz1lBvebouAvq1YLjSXw== X-Received: by 10.28.124.14 with SMTP id x14mr2711614wmc.85.1513102861549; Tue, 12 Dec 2017 10:21:01 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l25sm166982wmi.35.2017.12.12.10.21.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2017 10:21:00 -0800 (PST) Date: Tue, 12 Dec 2017 18:20:58 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171212182058.e7axjy2vyimeavih@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 0/8] SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 18:16:24 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Dec 12, 2017 at 10:37:59AM +0000, Ard Biesheuvel wrote: > A round of updates for Socionext SynQuacer: > > - enable CPU idle states in the DT, so that the OS can put cores to sleep > using PSCI (#1) > - add the build number to PCDs that end up in user visible strings (#2) > - fix a PCIe detection issue in the DeveloperBox x16 slot, by keeping PERST# > asserted for at least 100 ms before link training (#3) > - ignore PCIe RC #0 if no card is inserted on EVB (#4 - #6) > - add the secondary UART to the DT for the OS to use (this is UART #0 on the > LS connector on DeveloperBox) (#7) > - explicitly retrain the downstream links on the Asmedia 1182/1184 PCIe > switch, to enable Gen2 speeds For the patches I haven't commented on individually (1,4,6): Reviewed-by: Leif Lindholm > Ard Biesheuvel (7): > Silicon/SynQuacer: enable CPU idle states in device tree > Platform/Socionext/SynQuacer: expose build number as firmware version > Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# > Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting > Silicon/SynQuacer: disable PCI RC #0 DT node if disabled > Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected > Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed > > Masahisa KOJIMA (1): > Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the > OS > > Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 16 ++- > Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + > Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 18 ++- > Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + > Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 57 ++++---- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 94 +++++++++++++ > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 42 ++++++ > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 4 + > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 58 +++++--- > Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 +++++++--- > Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + > Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + > 19 files changed, 504 insertions(+), 88 deletions(-) > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h > create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > > -- > 2.11.0 >