From: Jian J Wang <jian.j.wang@intel.com>
To: edk2-devel@lists.01.org
Cc: Dandan Bi <dandan.bi@intel.com>, Eric Dong <eric.dong@intel.com>,
Laszlo Ersek <lersek@redhat.com>
Subject: [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names
Date: Mon, 25 Dec 2017 09:06:59 +0800 [thread overview]
Message-ID: <20171225010659.13428-5-jian.j.wang@intel.com> (raw)
In-Reply-To: <20171225010659.13428-1-jian.j.wang@intel.com>
Due to coding style fix of the structure definition in BaseLib.h, all
code referencing those structure must be updated accordingly.
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
.../Ia32/ArchExceptionHandler.c | 24 +++++++++++-----------
.../X64/ArchExceptionHandler.c | 6 +++---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 6ac8549839..4e89b0470f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -216,7 +216,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -240,7 +240,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -253,17 +253,17 @@ ArchSetupExcpetionStack (
continue;
}
- Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ Tss->Eip = (UINT32)(TemplateMap.ExceptionStart
+ Vector * TemplateMap.ExceptionStubHeaderSize);
- Tss->EFLAGS = 0x2;
- Tss->ESP = StackTop;
- Tss->CR3 = AsmReadCr3 ();
- Tss->ES = AsmReadEs ();
- Tss->CS = AsmReadCs ();
- Tss->SS = AsmReadSs ();
- Tss->DS = AsmReadDs ();
- Tss->FS = AsmReadFs ();
- Tss->GS = AsmReadGs ();
+ Tss->Eflags = 0x2;
+ Tss->Esp = StackTop;
+ Tss->Cr3 = AsmReadCr3 ();
+ Tss->Es = AsmReadEs ();
+ Tss->Cs = AsmReadCs ();
+ Tss->Ss = AsmReadSs ();
+ Tss->Ds = AsmReadDs ();
+ Tss->Fs = AsmReadFs ();
+ Tss->Gs = AsmReadGs ();
StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 1dcf4277de..4d52b4eb0e 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -186,7 +186,7 @@ ArchSetupExcpetionStack (
//
TssDesc = StackSwitchData->X64.ExceptionTssDesc;
Tss = StackSwitchData->X64.ExceptionTss;
- if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {
+ if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->Ist)) {
return EFI_INVALID_PARAMETER;
}
@@ -221,7 +221,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
@@ -236,7 +236,7 @@ ArchSetupExcpetionStack (
//
// Fixup IST
//
- Tss->IST[Index] = StackTop;
+ Tss->Ist[Index] = StackTop;
StackTop -= StackSwitchData->X64.KnownGoodStackSize;
//
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 0c2058a7b0..da1a43c430 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -243,7 +243,7 @@ RestoreVolatileRegisters (
VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr);
- if (Tss->Bits.P == 1) {
+ if (Tss->Bits.Present == 1) {
Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case
AsmWriteTr (VolatileRegisters->Tr);
}
--
2.15.1.windows.2
next prev parent reply other threads:[~2017-12-25 1:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-25 1:06 [PATCH 0/4] Coding style clean-up Jian J Wang
2017-12-25 1:06 ` [PATCH 1/4] MdePkg/BaseLib.h: " Jian J Wang
2017-12-25 1:51 ` Bi, Dandan
2017-12-25 2:23 ` Wang, Jian J
2017-12-25 1:06 ` [PATCH 2/4] MdeModulePkg/Core: " Jian J Wang
2017-12-25 1:19 ` Zeng, Star
2017-12-25 2:01 ` Bi, Dandan
2017-12-25 1:06 ` [PATCH 3/4] UefiCpuPkg/UefiCpuPkg.uni: Add missing string definition for new PCDs Jian J Wang
2017-12-25 1:58 ` Bi, Dandan
2017-12-25 2:28 ` Wang, Jian J
2017-12-25 1:06 ` Jian J Wang [this message]
2017-12-25 2:01 ` [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names Bi, Dandan
2017-12-26 16:47 ` [PATCH 0/4] Coding style clean-up Kinney, Michael D
2017-12-27 0:40 ` Wang, Jian J
2017-12-27 9:29 ` Gao, Liming
2017-12-27 16:35 ` Kinney, Michael D
2017-12-28 0:27 ` Wang, Jian J
2017-12-28 0:37 ` Kinney, Michael D
2017-12-28 0:53 ` Wang, Jian J
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