From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2707D21CB87A8 for ; Sun, 24 Dec 2017 17:02:14 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Dec 2017 17:07:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,452,1508828400"; d="scan'208";a="189773036" Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.64]) by fmsmga006.fm.intel.com with ESMTP; 24 Dec 2017 17:07:05 -0800 From: Jian J Wang To: edk2-devel@lists.01.org Cc: Dandan Bi , Eric Dong , Laszlo Ersek Date: Mon, 25 Dec 2017 09:06:59 +0800 Message-Id: <20171225010659.13428-5-jian.j.wang@intel.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20171225010659.13428-1-jian.j.wang@intel.com> References: <20171225010659.13428-1-jian.j.wang@intel.com> Subject: [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Dec 2017 01:02:14 -0000 Due to coding style fix of the structure definition in BaseLib.h, all code referencing those structure must be updated accordingly. Cc: Dandan Bi Cc: Eric Dong Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- .../Ia32/ArchExceptionHandler.c | 24 +++++++++++----------- .../X64/ArchExceptionHandler.c | 6 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 6ac8549839..4e89b0470f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -216,7 +216,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; - TssDesc->Bits.P = 1; + TssDesc->Bits.Present = 1; TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); @@ -240,7 +240,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; - TssDesc->Bits.P = 1; + TssDesc->Bits.Present = 1; TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); @@ -253,17 +253,17 @@ ArchSetupExcpetionStack ( continue; } - Tss->EIP = (UINT32)(TemplateMap.ExceptionStart + Tss->Eip = (UINT32)(TemplateMap.ExceptionStart + Vector * TemplateMap.ExceptionStubHeaderSize); - Tss->EFLAGS = 0x2; - Tss->ESP = StackTop; - Tss->CR3 = AsmReadCr3 (); - Tss->ES = AsmReadEs (); - Tss->CS = AsmReadCs (); - Tss->SS = AsmReadSs (); - Tss->DS = AsmReadDs (); - Tss->FS = AsmReadFs (); - Tss->GS = AsmReadGs (); + Tss->Eflags = 0x2; + Tss->Esp = StackTop; + Tss->Cr3 = AsmReadCr3 (); + Tss->Es = AsmReadEs (); + Tss->Cs = AsmReadCs (); + Tss->Ss = AsmReadSs (); + Tss->Ds = AsmReadDs (); + Tss->Fs = AsmReadFs (); + Tss->Gs = AsmReadGs (); StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index 1dcf4277de..4d52b4eb0e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -186,7 +186,7 @@ ArchSetupExcpetionStack ( // TssDesc = StackSwitchData->X64.ExceptionTssDesc; Tss = StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) { + if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->Ist)) { return EFI_INVALID_PARAMETER; } @@ -221,7 +221,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; - TssDesc->Bits.P = 1; + TssDesc->Bits.Present = 1; TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32); @@ -236,7 +236,7 @@ ArchSetupExcpetionStack ( // // Fixup IST // - Tss->IST[Index] = StackTop; + Tss->Ist[Index] = StackTop; StackTop -= StackSwitchData->X64.KnownGoodStackSize; // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 0c2058a7b0..da1a43c430 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -243,7 +243,7 @@ RestoreVolatileRegisters ( VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + VolatileRegisters->Tr); - if (Tss->Bits.P == 1) { + if (Tss->Bits.Present == 1) { Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case AsmWriteTr (VolatileRegisters->Tr); } -- 2.15.1.windows.2