From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 80EB5222CF1B4 for ; Wed, 10 Jan 2018 08:21:47 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id i11so90331wmf.4 for ; Wed, 10 Jan 2018 08:26:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=umC1O7ZWQTI4WXiKrrX0dODHPZstxnbx/nE7V0LWXmD4T6D42ZhzHi3LMcW7jzHQqw kMy2CfpwyeXRiiZTWYbGOecKlWmk7XrzTVhGfLznVZroCrf5MN/7ocHMdztRBnWlYrTF 341xq+KMmvnl4BEI/QCe/6hnQa2ihVadXVfAZzG6F5qw7yCQzuPK6uXKcNOHjseG4Fmq veCTG52ULYqkkt1Op7sb0AaVj5LpbhNYf8dgr6heVu8ovAUDKYozmunNH/4vZi4sN2HA ZEOgofZkLnFGHyAtm9mhlq3qApOgiRq431zUWd5qe1B7Ihf5GeKl3k3SmDdT17p/GWk3 RiOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=LQEDEa5E+3OLnvm6AiUF2SyNWNzsF2td63iAVxSzYj/6qye9AYUG4xH+0RlD16za6r 8qFVuxlmO3c1LIptL2kwUxyLEwv1ZOGoIBt8GpBiHdwYo1btBPcda7/IR+mQBkI/NGyB q3YrBjbcJ86pWtwF6/c2K0C87jAUNvprJzxCBS5InzgwNUP5utxlUPO6qNOr1M+Z1r0T yyElh5W6pb8NRDNiYGUkeqWeS1dr59sEhJNopNBzzBJ2xdup5KoN1k/0Kpr4iDraAd2Y NBorZllj8BsD2CUaK0bl+Wh5+U73VOGJnb6u3RsrdLrNX7TUKHcCNMzzmz76nBWt6kdv pJ4A== X-Gm-Message-State: AKwxytfdrFLEWryhGs+8Y+QAQ7Gj5oJ2nVsjRZsZdNHWGgU/brYLWMgi l1hjUNmjygqUniGyOkh5lgZJkrTaRc0= X-Google-Smtp-Source: ACJfBosKt1s06XHRNRfp8YZsbfy/QHru+LsqMOrWJTQzcNDssmBR8sAuJB/FaX0PeZfihEV0lntEPA== X-Received: by 10.80.245.10 with SMTP id t10mr3869629edm.168.1515601617284; Wed, 10 Jan 2018 08:26:57 -0800 (PST) Received: from localhost.localdomain ([84.203.41.108]) by smtp.gmail.com with ESMTPSA id a52sm10543021eda.92.2018.01.10.08.26.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 08:26:56 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org Date: Wed, 10 Jan 2018 16:26:41 +0000 Message-Id: <20180110162644.11208-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180110162644.11208-1-pete@akeo.ie> References: <20180110162644.11208-1-pete@akeo.ie> Subject: [PATCH v4 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jan 2018 16:21:48 -0000 Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..e7490b09d3dc 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ EXPORT CpuBreakpoint - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index fbfb0063b75f..3c07e6bad977 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -824,8 +824,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT - + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -834,7 +835,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT - + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC -- 2.9.3.windows.2