From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B0A5921D2BEE0 for ; Fri, 12 Jan 2018 05:28:31 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id t8so12105883wmc.3 for ; Fri, 12 Jan 2018 05:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=gNURxPnm2Rl7tgk9fuIGocnQdRvnmE2utOqoUzUGwBhp7kbE/F3zC49x+EHsG5/F73 JvauRrkOzIADmYhKXLQuYPhdY8HxDf04ArRs/jNlyiquCp37M16ApaBMCRngPn4XTE8Q XyghNnUOKYhQpbQYhG5vOjTg7qQDm+bT/+BiVLni80tQe/r5X6XBBinDB5H4EYjhSnY1 9qw6BcLf7rq9tHg55ZqCp3BiUEJWHjou7VxwQoJtSiTgKxUIl6EEVy4zRqzGLQ+Z1fuv FodYGpYTDmcrFb9eI5rrL2A1JZeQmugETtMVUHskFEwTaxYQamuzMCiXQQyxocK/UnJ4 UePw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=QFz0+n7rMIl1oJ1aI2oieiBpieQBK5UqV6YjBmnEaUcJXh9MlH7985Y2nDKCxdHXAe 4zYgkh34GvOL4U7HvqeySbEAYF101FfjguEqQrNbzSpWlsS6Od69X+KdNsy2nEi6ZbZK Rsx4m0RBfLzS+7uJ/LVQNUWDUJy2kttqBqFMNCRd1HPjppwTC9rhQ3ge4Lwpu8VOGcqz PVp1/m6u0kbN8er/poWnA2CfYuxGzbEMQpUULRIIhapJSX46vxbRHIxBns6f54Qih0Mz mX5jK+HaIoxfzO7So9Nsn25gwTQl582YQTg97cg9dlEqSLltFRpv9LAdEg403UD/ocHq Lizw== X-Gm-Message-State: AKGB3mLBWjn2HW5Xf5WuTbLL9O9ZAt2ZkQUuZ1Jh/WUF8NkXgM7NEsuw 9xaQtoPKqkWI2NT0juJQMdumqNh5rEs= X-Google-Smtp-Source: ACJfBotQ7uyMs5WyrDrtyxR36RnosIyftEO3shjhsBcJFxIhjhaGg0ZA8D0RA8RLs+vuchBTYfNQ5A== X-Received: by 10.80.226.139 with SMTP id p11mr37029661edl.151.1515764025150; Fri, 12 Jan 2018 05:33:45 -0800 (PST) Received: from localhost.localdomain ([84.203.42.225]) by smtp.gmail.com with ESMTPSA id c16sm1184952eda.67.2018.01.12.05.33.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Jan 2018 05:33:44 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org, eugene@hp.com Date: Fri, 12 Jan 2018 13:33:28 +0000 Message-Id: <20180112133331.7776-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180112133331.7776-1-pete@akeo.ie> References: <20180112133331.7776-1-pete@akeo.ie> Subject: [PATCH v5 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Jan 2018 13:28:32 -0000 Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..e7490b09d3dc 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ EXPORT CpuBreakpoint - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index fbfb0063b75f..3c07e6bad977 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -824,8 +824,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT - + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -834,7 +835,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT - + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC -- 2.9.3.windows.2