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From: Hao Wu <hao.a.wu@intel.com>
To: edk2-devel@lists.01.org
Cc: Hao Wu <hao.a.wu@intel.com>, Star Zeng <star.zeng@intel.com>,
	Ruiyu Ni <ruiyu.ni@intel.com>, Feng Tian <feng.tian@intel.com>
Subject: [PATCH] MdeModulePkg/NvmExpressDxe: Fix data buffer not mapped for Write cmd
Date: Tue, 23 Jan 2018 13:03:58 +0800	[thread overview]
Message-ID: <20180123050358.17840-1-hao.a.wu@intel.com> (raw)

Within function NvmExpressPassThru():

The data buffer for the below 2 Admin command:
Create I/O Completion Queue command (Opcode 01h)
Create I/O Submission Queue command (Opcode 05h)

are not mapped to the PCI controller specific addresses.

But the current code logic also prevents the below NVM command:
Write (Opcode 01h)

from mapping its data buffer.

Hence, this commit refine the logics to resolve this issue.

Cc: Star Zeng <star.zeng@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
 MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
index 7356c1d673..302cfdcd8d 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
@@ -3,7 +3,7 @@
   NVM Express specification.
 
   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
-  Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -593,7 +593,8 @@ NvmExpressPassThru (
   // these two cmds are special which requires their data buffer must support simultaneous access by both the
   // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
   //
-  if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
+  if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&
+      !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {
     if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {
       return EFI_INVALID_PARAMETER;
     }
-- 
2.12.0.windows.1



             reply	other threads:[~2018-01-23  4:58 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23  5:03 Hao Wu [this message]
2018-01-23  7:50 ` [PATCH] MdeModulePkg/NvmExpressDxe: Fix data buffer not mapped for Write cmd Zeng, Star
2018-01-23  8:39   ` Wu, Hao A

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