From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 28FB321E2568E for ; Thu, 25 Jan 2018 04:22:15 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id x4so30908762wmc.0 for ; Thu, 25 Jan 2018 04:27:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=eSYlf0goXwWYEccK7y8Oa/3LXCLv6c2k1gOQxSHGZfY=; b=crQ/S5JCvebZ9AnKNQXQbmRJfeIVH+kzT+FVhc3b/CdbfdxmadFGCW/rnBNjjUDwxI ksB4Q0KMirEDZzF9oP1O/o2a+OhuhsQwjDz6BNQerKoITb1nMl6HfNIwDj0EV3p/+aqT soHyI41WABYrz4rtgsRrhELsa7Co8M6ODKE5I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=eSYlf0goXwWYEccK7y8Oa/3LXCLv6c2k1gOQxSHGZfY=; b=LgL3gCVisvcF5WIX+P/ihvufDLm5HxI2mAbFw3W5JcfChWIXoDqrCLsUz0Wq5+vkai ZjVvUfJjEXD9biPuzEmYo1FaTAoVy4mdTH7ZS/bIcMyQAgI6oYCAvsc83UctGpcIEmFB kxw6Z1U5VR4gu0EZ7P0dHEohdfHbjZHIqbeKUjQYLt0LoJETQPgqOBYUs5nGNUGVsZN+ 6S5GFDdeLPfVY9eMV8yA3GzJG52mgRdVNTwmCAlGbFyRPUw+TE15TfiDCI98zCtEaPvQ QlofUrO/u4yV/aJfrY4Li6S6DmduZG/aIOUyzal84OvY6uuUL/xeTyksNdqawPppFtW6 vEuA== X-Gm-Message-State: AKwxytcOt3nZdmasNO71kZV1Idq7tr5SiiC4QF6ZOMyUWW8Uw0yBA98L WvIPUlVyZtLNIqALnpAoFJiQMYSbKVM= X-Google-Smtp-Source: AH8x224xp5oAtxPATCZfyRxSdttXWTbI7mkhcS1o2ui/91mevHGnLwhyZllQX635Z1qWl3ZVaLDUsw== X-Received: by 10.28.183.5 with SMTP id h5mr7620381wmf.14.1516883263747; Thu, 25 Jan 2018 04:27:43 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:42 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Thu, 25 Jan 2018 12:27:28 +0000 Message-Id: <20180125122736.5427-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH edk2-platforms 0/8] Socionext SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jan 2018 12:22:16 -0000 Some stuff I have collected over the past 2 months or so. Note that this includes the SATA spread spectrum patch I sent out yesterday: I had forgotten all about this backlog, and I only remembered when attempting to apply it to the master branch. Ard Biesheuvel (8): Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA Silicon: fix typo in gPcf8563RealTimeClockLibI2cMasterProtocolGuid Silicon/NXP/Pcf8563RealTimeClockLib: avoid driver binding protocol Silicon/SynQuacerI2cDxe: remove spurious format specifier Silicon/SynQuacer: load I2C driver before platform DXE driver Silicon/SynQuacer/DeviceTree: align uart DT nodes Silicon/SynQuacer/DeviceTree: update NETSEC DT node to latest binding Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 33 +++--- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 2 +- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 5 +- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 ++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 38 +++---- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Pci.c} | 85 +++++++++++---- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 109 +++++++++++++++++++- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 12 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 17 ++- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 28 +++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 61 +++++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 2 +- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 2 +- Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h | 23 +++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 28 +++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 2 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 25 ++++- Silicon/Socionext/SynQuacer/SynQuacer.dec | 7 ++ 21 files changed, 424 insertions(+), 73 deletions(-) rename Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Pci.c} (63%) create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr create mode 100644 Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h create mode 100644 Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h -- 2.11.0