From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2455421E25687 for ; Thu, 25 Jan 2018 04:53:11 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id i186so14410609wmi.4 for ; Thu, 25 Jan 2018 04:58:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=VqA8XWza3JQNG3l0zIE5/Fpo13nRAVlVN5TVGix8Fm4=; b=i/rdyxBJQkbTYFylGTOBkE31AoSDwK67gBKxWH6yTEiB+eCgKavv1tFZXLXyI7KDWf J0nljMUQT6RVfxDi/Rg50hyhol11qWt+/Va41fGJLd8sKVGsW4A5nTYD/zDh9pqNYLXY 2iBp2PWqgyUcAtBkfJh2HbMgp9pDdwoIzlzgw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VqA8XWza3JQNG3l0zIE5/Fpo13nRAVlVN5TVGix8Fm4=; b=p8RxtUvSX85TadEUzJ09Zon4+TKfyc14BsvUqkEt09FoE7UVdJDZrcwl5gQ1meB8S9 RKW+80PPM70uqeXQmPfnIgcRTysyEjs07e6ce//RLeRjevJCwl46RVTGQhwoz5Hha6r4 u3ZsBYLUdIWWo/ucks7HKEjhz0nBHSdEHypQKjI2NQOiC4epS7Qq0aw3W/ggvgN3rrpQ g/4WcJ4zupRkGBKjnSY8pDXnoIoOuHoxVPxZADpo1DgNuLhxWs8knPrgSf7D2N1k9lI0 08zDykkrYt4AO/zQVmdVMzSMDZNkv5g+rvk2R3vaPIkZyglNft0l7Y1Ak6X3dbcbw5WJ GoIQ== X-Gm-Message-State: AKwxytd7Hc9ZwUlpY8bK7ypbaoGwL14AX8yKNv2Xbs8X7oax7w8vp8w5 U8oOmWYgFxJBlXVplA2RrwINK3RfeCE= X-Google-Smtp-Source: AH8x226PQ4rA8uriiVABR3PGcz2HbxbDUNn3Pi06jHhFsCDY9mrcMdDFQiOZZOiy2rP2t+hNi3FczA== X-Received: by 10.28.67.194 with SMTP id q185mr7259455wma.76.1516885119158; Thu, 25 Jan 2018 04:58:39 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id h194sm1690830wma.8.2018.01.25.04.58.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jan 2018 04:58:38 -0800 (PST) Date: Thu, 25 Jan 2018 12:58:36 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20180125125836.cvjsvqvq2b4fq7kp@bivouac.eciton.net> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> <20180125122736.5427-7-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180125122736.5427-7-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/DeviceTree: align uart DT nodes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jan 2018 12:53:11 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jan 25, 2018 at 12:27:34PM +0000, Ard Biesheuvel wrote: > Align the UART DT nodes: > - use 'uart' not 'fuart' as node name for the second serial port > - create an alias 'serial1' for the second serial port > - use UART clock reference instead of hardcoded frequency > - split 'clocks' property into 1 cell per phandle > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 37a3981f0360..7c3518facb98 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -32,6 +32,7 @@ > > aliases { > serial0 = &soc_uart0; > + serial1 = &fuart; > }; > > chosen { > @@ -436,15 +437,16 @@ > compatible = "arm,pl011", "arm,primecell"; > reg = <0x0 0x2a400000 0x0 0x1000>; > interrupts = ; > - clocks = <&clk_uart &clk_apb>; > + clocks = <&clk_uart>, <&clk_apb>; > clock-names = "uartclk", "apb_pclk"; > }; > > - fuart: fuart@51040000 { > + fuart: uart@51040000 { > compatible = "snps,dw-apb-uart"; > reg = <0x0 0x51040000 0x0 0x1000>; > interrupts = ; > - clock-frequency = <62500000>; > + clocks = <&clk_uart>, <&clk_apb>; > + clock-names = "baudclk", "apb_pclk"; > reg-io-width = <4>; > reg-shift = <2>; > }; > -- > 2.11.0 >