From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8DCDC2215BD92 for ; Mon, 29 Jan 2018 06:45:35 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id f11so7515027wre.4 for ; Mon, 29 Jan 2018 06:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=dYFFJHG2aK2faBNwbcYLIKr+7QnN/DUxWRq9kPHMxxY=; b=Or7xA+0OoqcKwemQKxClDaESEJfTgNWOjhhVRqG9wX9LbLq/HOEEPquN3GaJpo9VBN rmwkNE5/EzUVC3U92ioUouUK1KO0fJXQKrY6hIloB/gxgQL9xc5rqi/BiIX66BHPSB93 7/82m7CBGrQgl4JgFdeUmRWYDMODaaEMqQRew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=dYFFJHG2aK2faBNwbcYLIKr+7QnN/DUxWRq9kPHMxxY=; b=TtPza23X25GOZ9RGeUwIbFlE10tpQ+D9caro7bOZGZsQ1A/51ZeeTH5DUUR8Pbf2Mg 1fi2I0R9Aca6vCU/hz2ZqPkUxG8ZTxZXyfYEYhs70jOQ6g2SrfOT00S8OYY8A98SsS3j aK5+I1AuGI6cOpXRn4W9PJr1yc8fZgzCq4QT5Jil8tzJN8ssKKi2Y4NJblOwMMXpDvuo z7J1n7Xh+jE+aSgSvOMNDhat7InJ2RKeDIEtKtTfM8cUNCi0J/ORF/HI+OteCPF2KpL1 BVvPPDF+euAuw0EDSoSu+3t59beQCZx8+Gu+fcQ4MzbQqeN/BD1DSJuWb5Hi37o23j/A UJqA== X-Gm-Message-State: AKwxyteoefP09dmpylS7BMe1jUbrhCVrAj7N//qo+cBJXqVxV+tESAjt X+SYnXqFB0bA54/JegFXn07BVA== X-Google-Smtp-Source: AH8x227zl/PdddJKmz2KyBSEnuU08AOMLpp9cmt0oDpLnKU3m/+gzC+bV3fwhQPqTSsYsLoiBHU7PA== X-Received: by 10.223.164.1 with SMTP id d1mr2406375wra.28.1517237467386; Mon, 29 Jan 2018 06:51:07 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id h200sm10181429wme.11.2018.01.29.06.51.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Jan 2018 06:51:06 -0800 (PST) Date: Mon, 29 Jan 2018 14:51:04 +0000 From: Leif Lindholm To: Thomas Abraham Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org Message-ID: <20180129145104.hwd4afi4l3kjf6an@bivouac.eciton.net> References: <1516986299-1616-1-git-send-email-thomas.abraham@arm.com> MIME-Version: 1.0 In-Reply-To: <1516986299-1616-1-git-send-email-thomas.abraham@arm.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] Platform/ARM/VExpress: refine the check for DVI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Jan 2018 14:45:36 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jan 26, 2018 at 10:34:59PM +0530, Thomas Abraham wrote: > The base models could have different values for the revision ID field > in the System ID register. Base models do not have support for DVI > and so the revision ID field should also be masked out when checking > for the presence of DVI support. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Thomas Abraham > --- > .../VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c > index 3f3ceb3..89ba130 100644 > --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c > +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c > @@ -264,7 +264,7 @@ LcdPlatformSetMode ( > SysId = MmioRead32 (ARM_VE_SYS_ID_REG); > if (SysId != ARM_RTSM_SYS_ID) { > // Take out the FVP GIC variant to reduce the permutations. > - SysId &= ~ARM_FVP_SYS_ID_VARIANT_MASK; > + SysId &= ~(ARM_FVP_SYS_ID_VARIANT_MASK | ARM_FVP_SYS_ID_REV_MASK); > if (SysId != ARM_FVP_BASE_BOARD_SYS_ID) { > // Set the DVI into the new mode > Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode); I think this change makes sense (and should arguably have been there from the start). But I also think it highlights that the surrounding comments are incorrect, and get increasingly confusing with this modification. I would suggest that // On the FVP models the GIC variant in encoded in bits [15:12]. is replaced by // On the FVP models, the build variant is encoded in bits [15:12]. and that // Take out the FVP GIC variant to reduce the permutations. is replaced by // Ignore build variant and revision. If you're happy with that, I can fold these changes to the surrounding comments in and commit. / Leif