From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 84EF521E25683 for ; Mon, 29 Jan 2018 09:27:37 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id d9so8148583wre.3 for ; Mon, 29 Jan 2018 09:33:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=znOwG0hJfJJPLe4SZ2qpZN245wgkRXk4xqYANPFqbk8=; b=NSPoP0eS8EkkSiQ1PK0FERwHb9CFK5FHsK2JYul5+vApzV5d8+rQeLR7Dii0MwkDbl F2jQJEWun/MTZXJGdkwdjA3AhRj+neynR50GomWm3+RefKbFMc+u8t3A+NeWYni8TUW3 z0WfKuw7UutBajvT62Z/FhFyLyW7Hd+ZbHvPo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=znOwG0hJfJJPLe4SZ2qpZN245wgkRXk4xqYANPFqbk8=; b=RjXoXgjOxL+4NiQKqrCOBgz4qwpxdBvgB8TokM4xXc0j1JlR2h9zGwMbff6GGbNxg6 kCJeJ2QARhJY+QoK30r7S+8rWZxbXokVdjb9CDR0gXJDyKIYNyb2HzftEjCnRAfXphkk omDAF15uFVHEZt5+2qIAU40cn6ULoArnkCkj2U/dILZq2cmPNTPG5PWpaBjbmmK5S4Zm wofb3hyTliryh8duwrkxDF3wa7ZLhmWtaUqXPcEZ+lakl4utqqefhnDCsX7AqxEbpT11 eYL0kIULHnpq0ta0Kdh/N7pCxTbfhEOUpAijSnrl9TeJG934/iZeurUnrHPNHZrM323g H6rA== X-Gm-Message-State: AKwxytcazMQaxQZEbKv9K4nEVub/obkZZtPe8Lr1YVDKBEfX1D2+3rK1 LTB3ECIVTVskKZgksnKtgY3jNQ== X-Google-Smtp-Source: AH8x227v0DqeCaYaVCZFhGevGn5tyHn9M7gv+SoIqb5oLjQxIfbuSPfqR78cN5zQuRRQEmwZyBBtBA== X-Received: by 10.223.196.129 with SMTP id m1mr12387037wrf.256.1517247189900; Mon, 29 Jan 2018 09:33:09 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id k125sm26645560wmd.48.2018.01.29.09.33.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Jan 2018 09:33:08 -0800 (PST) Date: Mon, 29 Jan 2018 17:33:07 +0000 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, mengfanrong@huawei.com, huangdaode@hisilicon.com, waip23@126.com, Jeremy Linton Message-ID: <20180129173307.e2pgjoxvmhvxmalx@bivouac.eciton.net> References: <1516953650-57980-1-git-send-email-huangming23@huawei.com> MIME-Version: 1.0 In-Reply-To: <1516953650-57980-1-git-send-email-huangming23@huawei.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Jan 2018 17:27:38 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline So, I'm mostly happy with this set, but: Sender (and hence Author for all patches that do not have a second From: statement after Subject: ) for all patches here is Ming Huang Can you please address this, either by actually sending from Ming Huang, or by adding a From:. You can add my Reviewed-by: Leif Lindholm to 3-4, 6-12 and 15. I have a few comments on 5/15, and then I need some input from others on the ACPI bits - especially from Jeremy, who should ideally have been cc:d on at least the PPTT patch given his comments on v1. / Leif On Fri, Jan 26, 2018 at 04:00:35PM +0800, Ming Huang wrote: > The major features of this patchset include > adding PPTT support, > switching to Generic BDS driver, > adding capsule upgrade support, > open-source version for SnpPlatform and SasPlatform > changing DmaLib to CoherentDmaLib(this one is omissive in v1). > > Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git > branch: rp-1802-platforms-v2 > > > Jason Zhang (3): > Hisilicon D03/D05: Add capsule upgrade support > Hisilicon D03/D05: Open SasPlatform source code > Hisilicon D03/D05: Open SnpPlatform source code > > Ming Huang (11): > Hisilicon/D05: Move Madt definition to head file > Hisilicon/D05: Add PPTT support > Hisilicon/D0x/BDS: Switch to Generic BDS driver > Hisilicon/D0x: Break BMC SetBoot option out into separate library > Hilisicon: Change DmaLib to CoherentDmaLib > Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table > Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver. > Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver. > Hisilicon/D05/ACPI: Add ITS PXM > Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM > Hisilicon D03/D05: Update firmware version to 18.02 > > Yan Zhang (1): > Hisilicon/PCIe: Disable PCIe ASPM > > Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ > Platform/Hisilicon/D03/D03.dsc | 42 +- > Platform/Hisilicon/D03/D03.fdf | 79 ++- > Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ > Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ > Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ > Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ > Platform/Hisilicon/D05/D05.dsc | 47 +- > Platform/Hisilicon/D05/D05.fdf | 80 ++- > Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ > Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ > Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ > Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++ > Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++ > Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +- > Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++ > Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++ > Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +- > Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++ > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 + > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 + > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +- > Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++ > Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 +++ > Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++ > Silicon/Hisilicon/HisiPkg.dec | 6 + > Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +- > Silicon/Hisilicon/Hisilicon.fdf.inc | 9 + > Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +- > Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 + > Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++ > Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 + > Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 + > Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + > Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++ > Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++ > Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++ > Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 + > Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++ > Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++ > Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++ > 46 files changed, 3536 insertions(+), 54 deletions(-) > create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini > create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc > create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf > create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c > create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini > create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc > create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf > create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c > create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c > create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf > create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c > create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf > create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c > create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h > create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf > create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h > create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h > create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h > create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h > create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c > create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf > create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c > create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h > create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf > create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c > create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf > > -- > 1.9.1 >