From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::22f; helo=mail-wm0-x22f.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x22f.google.com (mail-wm0-x22f.google.com [IPv6:2a00:1450:400c:c09::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 28BD82236488A for ; Tue, 30 Jan 2018 09:21:07 -0800 (PST) Received: by mail-wm0-x22f.google.com with SMTP id 141so2698775wme.3 for ; Tue, 30 Jan 2018 09:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=5ExWH6bhUiRXnJruHXleYJuZl/fgpcs4NdD1pRhTyoA=; b=AEARrOlDVikJ1hagZLRRu0aLPCW8f4KQqiNcQWKCtT+6/l7dCNL+UeX7WyP/P936Or zzssya/W3MC5YKCYK+rVfP0AEJOcX/PWHcM1GJQY2z3DXf8FAl1aoq65YzgbY46Ff8M6 AaA0nJCysMXoQyQh13c7oMTdiwng7cPIRyVAs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=5ExWH6bhUiRXnJruHXleYJuZl/fgpcs4NdD1pRhTyoA=; b=dhuPnInzTufbr6Bte/uSBNNGDgRKgfmQhC+7lPnPktNMWv1hTgLwbNSa3lluJPVRfQ RDOztjLi5oM+Hsz0VvZ7YpHU7CSaz6W9brP66WsGgdjrkcED6zPs3e7w4rdyky1dgFfK cUd2ZE7iEeqwWVTFy3fG4hw32Va3w5OANDEUMvDxuMc+Tt1OXLkogQvrtm00X11FyOOM 1z+ZZWEA37/OvBdV+8Y+ldFlYXMareKZzda3TEnU/dZLliKnC1bt5z0jQQXHq3JK8rTb U9ocyi4WIsknjVkRQFSfTbhlEF2E9Ina08WdSaodp/QaA03o7X/hK+wJEst+oFqBN2hA d7hA== X-Gm-Message-State: AKwxytdoEKOVpKR1KlowCmGOo+7FL0ca+WnmiQKku6UuIxyStewAXlvW Owrm/2IL3doxu9YVqElWxK7KVA== X-Google-Smtp-Source: AH8x227tnLq7HUj5iEv1p/21KHamZZvtZAiwTGGSx01FbT9Wmh4DLxX9WkZQ97acoEcIRPyOmT1Jbw== X-Received: by 10.28.150.139 with SMTP id y133mr12415879wmd.142.1517333201131; Tue, 30 Jan 2018 09:26:41 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id p12sm844537wre.83.2018.01.30.09.26.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 30 Jan 2018 09:26:39 -0800 (PST) Date: Tue, 30 Jan 2018 17:26:38 +0000 From: Leif Lindholm To: Marvin H?user Cc: "edk2-devel@lists.01.org" , Liming Gao , Michael D Kinney Message-ID: <20180130172638.4u2b3szkait2emaj@bivouac.eciton.net> References: MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: S3 wake restore operations, regarding S3IoLib and S3PciLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Jan 2018 17:21:08 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Not my area of expertise. Liming, Mike? On Tue, Jan 16, 2018 at 12:01:51AM +0000, Marvin H?user wrote: > Dear developers, > > First off, I'm writing this mail for educational purposes, so I > would be very thankful if I got a reply, though you will not miss > anything if you skip it. > > I was browsing several initialization codes of Intel platforms (the > ones included in the main edk2 repository, as well as MinPlatformPkg > from edk2-platforms), as well as recent imports of library code into > MdePkg (S3IoLib and S3PciLib). > While checking out latter, I noticed that all functions, including > 'And' and 'Or' operations, do not store the actual operations, but > just the value that results from applying them to the register at > the current time in execution. > While I checked out former, I noticed that actions are mixed (some > operations using SaveMemWrite, which saves the entire register's > value, some operations using SaveMemReadWrite, which saves the > operations (and/or) involved). > > Now, I do not have a lot of knowledge and/or experience with > low-level x86 initialization. I was checking out the PantherPoint > PCH specification, trying to find a clue on when to use which > operation precisely. Every register (be it a MMIO or PCI register) I > was looking at (with a few exceptions, as I have just noticed), had > a clear, defined value upon power-up. I'm also certain that there > are no conditional executions possible by the BootScript table, > which makes me think that storing the and/or operations and storing > just the register values is basically achieving the same state in > the end. > > I hope for your experience regarding the following questions: > > 1. Is my quite poorly researched assumption that there is no > actual difference between these two types of operation (for > registers with a clearly defined default value) usually/always > correct (for x86 platforms)? > * If they are, why are there different opcodes in the > BootScript table? To support platforms for which that is > not the case? > * If they are not, how could one be sure on what to use? > Which specification or datasheet contains the necessary > information? Is S3*Lib safe to use without explicate > knowledge? > * If they are not, can there be a drawback to always storing > the and/or operations to apply, such as applying the > operations on a random register value (undefined default > value)? > > i. If there is no drawback, why are the S3*Libs using the method of storing the final value rather than the operation? > > 1. Just after composing the questions, I noticed two registers > that indeed do not have a defined power-up value. In that > case, I wonder whether it is unsafe to run a complete write, > as it overwrites whatever is there (it's unpredictable, I > suppose), or whether it is unsafe to use the and/or > operations, as there may be unwanted bits set due to the > undefined value. > > Thank you in advance for your time, if you have read till here! > > Best regards, > Marvin. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel