From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48F94223AF829 for ; Fri, 2 Feb 2018 06:34:57 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 56D374E907; Fri, 2 Feb 2018 14:40:35 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-50.rdu2.redhat.com [10.10.121.50]) by smtp.corp.redhat.com (Postfix) with ESMTP id 559B66765F; Fri, 2 Feb 2018 14:40:33 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Eric Dong , Jiewen Yao , Liming Gao , Michael D Kinney , Ruiyu Ni Date: Fri, 2 Feb 2018 15:39:53 +0100 Message-Id: <20180202143954.7357-14-lersek@redhat.com> In-Reply-To: <20180202143954.7357-1-lersek@redhat.com> References: <20180202143954.7357-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 02 Feb 2018 14:40:35 +0000 (UTC) Subject: [PATCH 13/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 14:34:57 -0000 Rename the variable to "gPatchSmmInitStack" so that its association with PatchInstructionX86() is clear from the declaration, change its type to UINT8, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmmInit.nasm". The size of the patched source operand is (sizeof (UINTN)). Cc: Eric Dong Cc: Jiewen Yao Cc: Liming Gao Cc: Michael D Kinney Cc: Ruiyu Ni Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 6 +++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 6 +++--- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index 5095c41af45e..d38d4782187f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -302,7 +302,7 @@ extern UINT32 mSmmCr0; extern UINT8 gPatchSmmCr3; extern UINT32 mSmmCr4; extern UINT8 gPatchSmmCr4; -extern UINTN gSmmInitStack; +extern UINT8 gPatchSmmInitStack; /** Semaphore operation for all processor relocate SMMBase. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index 0609ed3738c7..501ebf0ed13f 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -848,7 +848,11 @@ PiCpuSmmEntry ( // // Set SMI stack for SMM base relocation // - gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)); + PatchInstructionX86 ( + &gPatchSmmInitStack, + (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)), + sizeof (UINTN) + ); // // Initialize IDT diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm index f59413d9d4a3..5ff3cd2e731f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress) global ASM_PFX(gPatchSmmCr3) global ASM_PFX(gPatchSmmCr4) global ASM_PFX(gPatchSmmCr0) -global ASM_PFX(gSmmInitStack) +global ASM_PFX(gPatchSmmInitStack) global ASM_PFX(gcSmiInitGdtr) global ASM_PFX(gcSmmInitSize) global ASM_PFX(gcSmmInitTemplate) @@ -72,8 +72,8 @@ BITS 32 mov fs, edi mov gs, edi mov ss, edi - DB 0xbc ; mov esp, imm32 -ASM_PFX(gSmmInitStack): DD 0 + mov esp, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmmInitStack): call ASM_PFX(SmmInitHandler) rsm diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm index 2460e1eb2dee..eae14c0549f0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress) global ASM_PFX(gPatchSmmCr3) global ASM_PFX(gPatchSmmCr4) global ASM_PFX(gPatchSmmCr0) -global ASM_PFX(gSmmInitStack) +global ASM_PFX(gPatchSmmInitStack) global ASM_PFX(gcSmiInitGdtr) global ASM_PFX(gcSmmInitSize) global ASM_PFX(gcSmmInitTemplate) @@ -72,8 +72,8 @@ ASM_PFX(gPatchSmmCr0): BITS 64 @LongMode: ; long-mode starts here - DB 0x48, 0xbc ; mov rsp, imm64 -ASM_PFX(gSmmInitStack): DQ 0 + mov rsp, strict qword 0 ; source operand will be patched +ASM_PFX(gPatchSmmInitStack): and sp, 0xfff0 ; make sure RSP is 16-byte aligned ; ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save -- 2.14.1.3.gb7cf6e02401b